MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 287

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CSn_BNDS are shown in
Table 8-6
8.4.1.2
The chip select configuration (CSn_CONFIG) registers shown in
and set the number of row and column bits used for each chip select. These registers should be loaded with
the correct number of row and column bits for each SDRAM. Because CSn_CONFIG[ROW_BITS_CS_n,
COL_BITS_CS_n] establish address multiplexing, the user should take great care to set these values
correctly.
If chip select interleaving is enabled, then all fields in the lower interleaved chip select are used, and the
other registers’ fields are unused, with the exception of the ODT_RD_CFG and ODT_WR_CFG fields.
For example, if chip selects 0 and 1 are interleaved, all fields in CS0_CONFIG are used, but only the
ODT_RD_CFG and ODT_WR_CFG fields in CS1_CONFIG are used.
Freescale Semiconductor
Offset 0x080, 0x084, 0x088, 0x08C
Reset
Reset
Offset 0x000, 0x008, 0x010, 0x018
Reset
16–19
20–31
4–15
Bits
0–3
W
W
W
R
R
R
CS_ n _ EN
BA_BITS_CS_ n
0
Name
SA n
EA n
describes the CSn_BNDS register fields.
—
—
16
0
—
Chip Select Configuration (CS n _CONFIG)
Reserved
Starting address for chip select (bank) n. This value is compared against the 12 msbs of the 36-bit address.
Reserved
Ending address for chip select (bank) n. This value is compared against the 12 msbs of the 36-bit address.
3
17
1
4
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 8-3. Chip Select Configuration Register (CS n _CONFIG)
18
Figure 8-2. Chip Select Bounds Registers (CS n _BNDS)
Figure
—
Table 8-6. CS n_ BNDS Field Descriptions
8-2.
SA n
—
20
ROW_BITS_CS_ n
21
All zeros
All zeros
All zeros
23
7
15 16
Description
AP_ n _EN
24
8
—
Figure 8-3
19 20
ODT_RD_CFG
9
—
enable the DDR chip selects
11
—
12
28
EA n
DDR Memory Controller
Access: Read/Write
Access: Read/Write
COL_BITS_CS_ n
ODT_WR_CFG
13
29
8-13
15
31
31