MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1348

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21-14
31–16
Bits
15
14
13
12
11
10
9
8
7
6
Name
ULPII
HCH
RCL
SRI
URI
SLI
AS
PS
—
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved, should be cleared.
Asynchronous schedule status. Reports the current real status of the asynchronous schedule. The
USB controller is not required to immediately disable or enable the asynchronous schedule when
software transitions USBCMD[ASE]. When this bit and USBCMD[ASE] have the same value, the
asynchronous schedule is either enabled (1) or disabled (0). Only used in host mode.
0 Disabled
1 Enabled
Periodic schedule status. Reports the current real status of the periodic schedule. The USB controller
is not required to immediately disable or enable the periodic schedule when software transitions
USBCMD[PSE]. When this bit and USBCMD[PSE] have the same value, the periodic schedule
is either enabled (1) or disabled (0). Only used in host mode.
0 Disabled
1 Enabled
Reclamation. Used to detect an empty asynchronous schedule. Only used by the host mode.
0 Non-empty asynchronous schedule
1 Empty asynchronous schedule
HC haIted. This bit is a zero whenever USBCMD[RS] is a one. The USB controller sets this bit to one
after it has stopped executing because of USBCMD[RS] being cleared, either by software or by the
host controller hardware (for example, internal error). Only used in host mode.
0 Running
1 Halted
Reserved, should be cleared.
ULPI interrupt. An event completion to the viewport register sets this bit. If the ULPI enables the
USBINTR[ULPIE] to be set, the USB interrupt (UI) will occur.
Reserved, should be cleared.
DCSuspend. This is a non-EHCI bit. When a device controller enters a suspend state from an active
state, this bit is set. The device controller clears the bit upon exiting from a suspend state. Only used
by the device controller.
0 Active
1 Suspended
Host mode:
Device mode:
Software writes a 1 to this bit to clear it.
USB reset received. This is a non-EHCI bit. When the USB controller detects a USB reset and enters
the default state, this bit will be set. Software can write a 1 to this bit to clear the USB reset received
status bit. Only used by the device mode.
0 No reset received
1 Reset received
• This is a non-EHCI status bit. In host mode, this bit will be set every 125 us, provided the PHY clock
• SOF received. When the USB controller detects a Start Of (micro) Frame, this bit will be set. When
is present and running (for example, the port is NOT suspended), and can be used by the host
controller driver as a time base.
a SOF is extremely late, the USB controller will automatically set this bit to indicate that an SOF
was expected. Therefore, this bit will be set roughly every 1 msec in device FS mode and every 125
msec in HS mode and will be synchronized to the actual SOF that is received. Because the
controller is initialized to FS before connect, this bit will be set at an interval of 1 msec during the
prelude to the connect and chirp.
Table 21-10. USBSTS Register Field Descriptions
Description
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