MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1704

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

T–U
Soft reset, 23-27, 23-28
SPCOM,, 18-9
SPI command register,, 18-7
SPI event register,, 18-6, 18-7
SPI,, 18-1
Split transaction isochronous transfer descriptor (siTD), see
Split transactions, see USB interface, split transactions
SRAM, see L2 cache/SRAM, 6-27
SRESET (soft reset) signal, 4-2, 4-8
Stashing, see L2 cache/SRAM, stashing, 6-25
SYSCLK (system clock input) signal, 4-3
System interface, 21-40
T
TA (LBC data transfer acknowledge) signal, 13-45
Target-disconnect, see PCI/PCI-X controller
TCK (JTAG test clock) signal, 25-8
TCR (timer control register), see e500 core, registers
TDI (JTAG test data input) signal, 25-8
TDO (JTAG test data output) signal, 25-8
Termination
Index-18
PIC
reset
USB interface, 21-2–21-4
watchpoint monitor
PCI/PCI-X, termination of PCI transactions, 16-52
PCI_AD[63:0] (address/data bus), 16-6
PCI_C/BE[7:0] (command/byte enable), 16-7, 16-46,
PCI_DEVSEL (device select), 16-7, 16-48
PCI_FRAME (frame), 16-7, 16-45
PCI_GNT[4:0] (bus grant), 16-8, 16-42
PCI_IDSEL (initialization device), 16-8
PCI_IRDY (intitiator ready), 16-8, 16-45
PCI_PAR (parity), 16-9
PCI_PERR (parity error), 16-9, 16-66
PCI_REQ[4:0] (bus request), 16-9, 16-42
PCI_SERR (system error), 16-10, 16-66
PCI_STOP (stop), 16-10, 16-49
PCI_TRDY (target ready), 16-10, 16-45
IRQ[0:11], 9-8
IRQ_OUT, 9-8, 9-28
MCP, 9-8
HRESET (hard reset), 4-2, 4-8
HRESET_REQ (hard reset request), 4-2, 11-18, 11-19
READY, 4-2, 25-23, 25-24
SRESET (soft reset), 4-2, 4-8
see also USB interface, signals
TRIG_IN (watchpoint trigger in), 25-7, 25-11, 25-17
TRIG_OUT (watchpoint trigger out), 25-8, 25-23
USB interface, split transaction isochronous transfer
descriptor (siTD)
16-48, 16-49, 16-65
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Test interface, see JTAG test access port
TEST_SEL (factory test) signal, 25-6
THERM[0:1] (thermal resistor access) signals, 25-9
Timing diagrams
TMS (JTAG test mode select) signal, 25-8
Trace buffer
Transactions
TRIG_IN (watchpoint trigger in) signal, 25-7, 25-11, 25-17
TRIG_OUT (watchpoint trigger out) signal, 25-8, 25-23
TRST (JTAG test reset) signal, 25-9
TSECn_COL (eTSEC 1–4 collision input) signals, 14-10
TSECn_CRS (eTSEC 1–4 carrier sense input/FIFO receiver
TSECn_GTX_CLK (eTSEC 1–4 gigabit transmit clock)
TSECn_RX_CLK (eTSEC 1–4 receive clock) signals, 14-11
TSECn_RX_DV (eTSEC 1–4 receive data valid) signals,
TSECn_RX_ER (eTSEC 1–4 receive error) signals, 14-12
TSECn_RXD[7:0] (eTSEC 1–4 receive data in) signals,
TSECn_TX_CLK (eTSEC 1–4 transmit clock in) signals,
TSECn_TX_EN (eTSEC 1–4 transmit data valid) signals,
TSECn_TX_ER (eTSEC 1–4 transmit error) signals, 14-13
TSECn_TXD[7:0] (eTSEC 1–4 transmit data out) signals,
U
UART_CTS[0:1] (DUART clear to send) signals, 12-1, 12-3
UART_RTS[0:1] (DUART request to send) signals, 12-1,
UART_SIN [0:1] (DUART transmitter serial data in) signals,
UART_SOUT [0:1] (DUART transmitter serial data out)
PCI/PCI-X transactions, 16-50
and watchpoint monitor, block diagram, 25-1
as a second watchpoint monitor, 25-27
functional description, 25-27–25-29
initialization, 25-30
modes of triggering and arming, 25-4
overview, 25-1
register descriptions, 25-15–25-22
see also Watchpoint monitor, 25-4
traced data formats relative to TBCR1[IFSEL]
PCI/PCI-X see PCI/PCI-X controller, transactions
by acronym, see Register Index
DDR trace buffer entry, 25-28
ECM trace buffer entry, 25-27
PCI trace buffer entry, 25-28, 25-29
flow control) signals, 14-10
signals, 14-10
14-11
14-12
14-12
14-13
14-13
12-3
12-2, 12-3
signals, 12-2, 12-3
Freescale Semiconductor
Index