MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1627

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A.1.11
Freescale Semiconductor
0xE38–
0x000–
0x000–
0xC0C
Offset
0xE2C
0xFFC
0xFFC
0xFFC
Offset
0xC00
0xC04
0xC08
0xC10
0xC14
0xE20
0xE24
0xE28
0xE30
0xE34
General-Purpose I/O (GPIO)
PEX_ERR_CAP_STAT—PCI Express error capture status
register
Reserved
PEX_ERR_CAP_R0—PCI Express error capture register 0
PEX_ERR_CAP_R1—PCI Express error capture register 1
PEX_ERR_CAP_R2—PCI Express error capture register 2
PEX_ERR_CAP_R3—PCI Express error capture register 3
Reserved
PCI Express Controller 2 registers
Note: All registers defined for PCI Express Controller 1 are also defined for PCI Express Controller 2; the offsets
PCI Express Controller 3 registers
Note: All registers defined for PCI Express Controller 1 are also defined for PCI Express Controller 3; the offsets
GPIO direction register (GPDIR)
GPIO open drain register (GPODR)
GPIO data register (GPDAT)
GPIO interrupt event register (GPIER)
GPIO interrupt mask register (GPIMR)
GPIO external interrupt control register (GPICR)
of PCI Express Controller 2 registers are the same except they have a different block base address.
of PCI Express Controller 3 registers are the same except they have a different block base address.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table A-10. PCI Express Controller 1 & 2 Registers (continued)
PCI Express Controller 1—Block Base Address 0x0_A000
PCI Express Controller 3—Block Base Address 0x0_B000
PCI Express Controller 2—Block Base Address 0x0_9000
PCI Express Controller 2 Memory-Mapped Registers
PCI Express Controller 3 Memory-Mapped Registers
Register
Register
Table A-11. GPIO Registers
Complete List of Configuration, Control, and Status Registers
Access
Access
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Undefined
Reset
Reset
—
—
17.3.6.4/17-36
17.3.6.5/17-36
17.3.6.6/17-38
17.3.6.7/17-40
17.3.6.8/17-42
Section/Page
Section/Page
22.3.1/22-2
22.3.2/22-3
22.3.3/22-3
22.3.4/22-4
22.3.5/22-4
22.3.6/22-5
—
A-15