MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 695

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The timing diagram in
13.4.2.3.1
The GPCM supports internal generation of transfer acknowledge. It allows between zero and 30 wait states
to be added to an access by programming ORn[SCY] and ORn[TRLX]. Internal generation of transfer
acknowledge is enabled if ORn[SETA] = 0. If LGTA is asserted externally two bus clock cycles or more
before the wait state counter has expired (to allow for synchronization latency), the current memory cycle
is terminated by LGTA; otherwise it is terminated by the expiration of the wait state counter. Regardless
of the setting of ORn[SETA], wait states prolong the assertion duration of both LOE and LWEn in the same
manner. When TRLX = 1, the number of wait states inserted by the memory controller is doubled from
ORn[SCY] cycles to 2×ORn[SCY] cycles, allowing a maximum of 30 wait states.
13.4.2.3.2
Figure 13-34
LCSn is connected directly to CE of the memory device. The LWE[0:3] signals are connected to the
respective WE[3:0] signals on the memory device where each LWE[0:3] signal corresponds to a different
data byte.
As
transaction are supplied by LOE or LWEn, depending on the transaction direction—read or write (write
case shown in the figure). ORn[CSNT], along with ORn[TRLX], control the timing for the appropriate
Freescale Semiconductor
Figure 13-38
•
•
•
•
•
One quarter of a clock cycle later.
One half of a clock cycle later.
One clock cycle later (for LCRR[CLKDIV] = 2 (clock ratio of 4)), when ORn[XACS] = 1.
Two clock cycles later, when ORn[XACS] = 1.
Three clock cycles later, when ORn[XACS] = 1 and ORn[TRLX] = 1.
shows a basic connection between the local bus and a static memory device. In this case,
LWE n
LCLK
LCS n
LALE
Programmable Wait State Configuration
Chip-Select and Write Enable Negation Timing
LAD
LOE
TA
shows, the timing for LCSn is the same as for the latched address. The strobes for the
A
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 13-35
Address
(XACS = 0, ACS = 00, CSNT = 1, SCY = 1, TRLX = 0)
Figure 13-38. GPCM Basic Write Timing
shows two chip-select assertion timings.
Latched Address
Write Data
SCY = 1
CSNT = 1
Enhanced Local Bus Controller
13-53