MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 588

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.8.5
The RNGU interrupt status register indicates which unmasked errors have occurred and have generated
error interrupts to the channel. Each bit in this register can only be set if the corresponding bit of the RNGU
interrupt mask register is zero (see
If the RNGU interrupt status register is non-zero, the RNGU halts and the RNGU error interrupt signal is
asserted to the controller (see
RNGU is being operated through channel-controlled access, then an interrupt signal is generated to the
channel to which this EU is assigned. The EU error then appears in bit 55 of the Channel Pointer Status
Register (see
If the interrupt status register is written from the host, 1s in the value written are recorded in the interrupt
status register if the corresponding bit is unmasked in the interrupt mask register. All other bits are cleared.
This register can also be cleared by setting the RI bit of the RNGU Reset Control Register.
The bit fields of the RNGU interrupt status register are shown in
10-158
59–60
Bits
58
61
62
63
RNGU Interrupt Status Register
Table
Name
HALT
RD
—
EI
DI
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
10-15) and generates a channel error interrupt to the controller.
Table 10-73. RNGU Status Register Field Descriptions (continued)
Halt. Indicates that the RNGU has halted due to an error.
0 RNGU not halted
1 RNGU halted
Note: Because the error causing the RNGU to stop operating may be masked before
reaching the interrupt status register, the RNGU interrupt status register is used to provide
a second source of information regarding errors preventing normal operation.
Reserved
Error interrupt: This status bit reflects the state of the error interrupt signal, as sampled by
the Controller interrupt status register
(ISR)”).
0 RNGU is not signaling error
1 RNGU is signaling error
Done interrupt: This status bit reflects the state of the done interrupt signal, as sampled by
the controller interrupt status register
(ISR)”).
0 RNGU is not signaling done
1 RNGU is signaling done
Reset Done. This status bit, when high, indicates that the RNGU has completed its reset
sequence.
0 Reset in progress
1 Reset done
Note: Reset Done resets to 0, but has typically switched to 1 by the time a user checks the
Section 10.5.4.2.2, “Interrupt Status Register
register, indicating the EU is ready for operation.
Section 10.7.8.6, “RNGU Interrupt Mask
(Section 10.5.4.2.2, “Interrupt Status Register
(Section 10.5.4.2.2, “Interrupt Status Register
Description
Figure
10-107.
(ISR)”). In addition, if the
Register”).
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