MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 43

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
21.3.1.3
21.3.1.4
21.3.1.5
21.3.1.6
21.3.2
21.3.2.1
21.3.2.2
21.3.2.3
21.3.2.4
21.3.2.5
21.3.2.6
21.3.2.7
21.3.2.8
21.3.2.9
21.3.2.10
21.3.2.11
21.3.2.12
21.3.2.13
21.3.2.14
21.3.2.15
21.3.2.16
21.3.2.17
21.3.2.18
21.3.2.19
21.3.2.20
21.3.2.21
21.3.2.22
21.3.2.23
21.3.2.24
21.3.2.25
21.3.2.26
21.3.2.27
21.4
21.4.1
21.4.2
21.4.3
21.4.4
21.5
21.5.1
21.5.2
21.5.3
Freescale Semiconductor
Functional Description................................................................................................. 21-40
Host Data Structures .................................................................................................... 21-41
Operational Registers............................................................................................... 21-10
System Interface ...................................................................................................... 21-40
DMA Engine............................................................................................................ 21-40
FIFO RAM Controller ............................................................................................. 21-41
PHY Interface .......................................................................................................... 21-41
Periodic Frame List.................................................................................................. 21-42
Asynchronous List Queue Head Pointer.................................................................. 21-43
Isochronous (High-Speed) Transfer Descriptor (iTD)............................................. 21-44
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Host Controller Structural Parameters (HCSPARAMS) ....................................... 21-7
Device Controller Interface Version (DCIVERSION)—Non-EHCI..................... 21-9
USB Command Register (USBCMD) ................................................................. 21-11
USB Status Register (USBSTS) .......................................................................... 21-13
USB Interrupt Enable Register (USBINTR) ....................................................... 21-15
Frame Index Register (FRINDEX)...................................................................... 21-17
Control Data Structure Segment Register (CTRLDSSEGMENT)...................... 21-18
Periodic Frame List Base Address Register (PERIODICLISTBASE)................ 21-18
Device Address Register (DEVICEADDR)—Non-EHCI .................................. 21-19
Current Asynchronous List Address Register (ASYNCLISTADDR)................. 21-19
Endpoint List Address Register (ENDPOINTLISTADDR)—Non-EHCI .......... 21-20
Master Interface Data Burst Size Register (BURSTSIZE)—Non-EHCI ............ 21-21
Transmit FIFO Tuning Controls Register (TXFILLTUNING)—Non-EHCI...... 21-21
ULPI Register Access (ULPI VIEWPORT)........................................................ 21-23
Configure Flag Register (CONFIGFLAG).......................................................... 21-24
Port Status and Control Register (PORTSC) ....................................................... 21-25
USB Mode Register (USBMODE)—Non-EHCI ................................................ 21-29
Endpoint Setup Status Register (ENDPTSETUPSTAT)—Non-EHCI ................ 21-30
Endpoint Initialization Register (ENDPTPRIME)—Non-EHCI......................... 21-31
Endpoint Flush Register (ENDPTFLUSH)—Non-EHCI .................................... 21-32
Endpoint Status Register (ENDPTSTATUS)—Non-EHCI ................................. 21-32
Endpoint Complete Register (ENDPTCOMPLETE)—Non-EHCI..................... 21-33
Endpoint Control Register 0 (ENDPTCTRL0)—Non-EHCI .............................. 21-33
Endpoint Control Register n (ENDPTCTRLn)—Non-EHCI .............................. 21-35
SNOOP1 and SNOOP2—Non-EHCI.................................................................. 21-36
Age Count Threshold Register (AGE_CNT_THRESH)—Non-EHCI ............... 21-37
Priority Control Register (PRI_CTRL)—Non-EHCI.......................................... 21-38
System Interface Control Register (SI_CTRL)—Non-EHCI.............................. 21-39
USB General Purpose Register (CONTROL)—Non-EHCI................................ 21-39
Host Controller Capability Parameters (HCCPARAMS) ...................................... 21-8
Device Controller Capability Parameters (DCCPARAMS)—Non-EHCI........... 21-10
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