MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 347

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Single-beat writes are performed by masking the last three (or seven) beats of the four- (or eight-) beat
burst using the data mask MDM[0:8]. If ECC is disabled, writes smaller than double words are performed
by appropriately activating the data mask. If ECC is enabled, the controller performs a read-modify write.
To accommodate available memory technologies across a wide spectrum of operating frequencies, the
DDR memory controller allows the setting of the intervals defined in
memory clock cycle, except for CASLAT, which can be programmed with 1/2 clock granularity.
Freescale Semiconductor
WR_DATA_DELAY
Timing Intervals
ACTTOPRE
ACTTOACT
PRETOACT
ACTTORW
BSTOPRE
WRTORD
REFREC
CASLAT
WRREC
REFINT
If a second read or write is pending, reads shorter than four beats are not
terminated early even if some data is irrelevant.
The number of clock cycles from a bank-activate command until another bank-activate command within
a physical bank. This interval is listed in the AC specifications of the SDRAM as t
The number of clock cycles from an activate command until a precharge command is allowed. This
interval is listed in the AC specifications of the SDRAM as t
The number of clock cycles from an activate command until a read or write command is allowed. This
interval is listed in the AC specifications of the SDRAM as t
The number of clock cycles to maintain a page open after an access. The page open duration counter
is reloaded with BSTOPRE each time the page is accessed (including page hits). When the counter
expires, the open page is closed with an SDRAM precharge bank command as soon as possible.
Used in conjunction with additive latency to obtain the READ latency. The number of clock cycles
between the registration of a READ command by the SDRAM and the availability of the first piece of
output data. If a READ command is registered at clock edge
data is available nominally coincident with clock edge
allowed. This interval is listed in the AC specifications of the SDRAM as t
Refresh interval. Represents the number of memory bus clock cycles between refresh cycles.
Depending on DDR_SDRAM_CFG_2[NUM_PR], some number of rows are refreshed in each SDRAM
bank during each refresh cycle. The value of REFINT depends on the specific SDRAMs used and the
frequency of the interface as t
be calculated by referring to the AC specification of the SDRAM device. The AC specification indicates
a maximum refresh-to-activate interval in nanoseconds.
Provides different options for the timing between a write command and the write data strobe. This allows
write data to be sent later than the nominal time to meet the SDRAM timing requirement between the
registration of a write command and the reception of a data strobe associated with the write command.
The specification dictates that the data strobe may not be received earlier than 75% of a cycle, or later
than 125% of a cycle, from the registration of a write command. This parameter is not defined in the
SDRAM specification. It is implementation-specific, defined for the DDR memory controller in
TIMING_CFG_2.
The number of clock cycles from the last beat of a write until a precharge command is allowed. This
interval, write recovery time, is listed in the AC specifications of the SDRAM as t
Last write pair to read command. Controls the number of clock cycles from the last write data pair to the
subsequent read command to the same bank as t
The number of clock cycles from a precharge command until an activate or a refresh command is
The number of clock cycles from the refresh command until an activate command is allowed. This can
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-62. DDR SDRAM Interface Timing Intervals
RP
.
NOTE
Definition
WTR
n
.
+
m
RAS
RCD
Table 8-62
n
.
, and the read latency is
.
.
RP
with granularity of one
.
WR
DDR Memory Controller
RRD
.
.
m
clocks, the
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