MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 68

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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15-1
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lxviii
Status Register Definition ................................................................................................. 14-137
AN Advertisement Register Definition............................................................................. 14-138
AN Link Partner Base Page Ability Register Definition .................................................. 14-140
AN Expansion Register Definition ................................................................................... 14-141
AN Next Page Transmit Register Definition .................................................................... 14-141
AN Link Partner Ability Next Page Register Definition .................................................. 14-142
Extended Status Register Definition ................................................................................. 14-143
Jitter Diagnostics Register Definition ............................................................................... 14-144
TBI Control Register Definition ....................................................................................... 14-145
eTSEC-MII Connection .................................................................................................... 14-146
eTSEC-RMII Connection ................................................................................................. 14-147
eTSEC-GMII Connection ................................................................................................. 14-148
eTSEC-RGMII Connection............................................................................................... 14-149
eTSEC-TBI Connection .................................................................................................... 14-150
eTSEC-RTBI Connection ................................................................................................. 14-151
eTSEC-FIFO (8-Bit) Connection...................................................................................... 14-158
8-Bit GMII-Style Packet FIFO Timing ............................................................................. 14-158
8-Bit Encoded Packet FIFO Timing ................................................................................. 14-159
Definition of Custom Preamble Sequence ........................................................................ 14-165
Definition of Received Preamble Sequence...................................................................... 14-166
Ethernet Address Recognition Flowchart ......................................................................... 14-167
Sample C Code for Computing eTSEC Hash Table Indices............................................. 14-169
Location of Frame Control Blocks for TOE Parameters .................................................. 14-177
Transmit Frame Control Block ......................................................................................... 14-178
Receive Frame Control Block........................................................................................... 14-179
Structure of the Receive Queue Filer Table ...................................................................... 14-184
1588 Timer Design Partition ............................................................................................. 14-195
Ethernet Sampling Points for 1588 ................................................................................... 14-195
PTP Packet Format............................................................................................................ 14-197
Buffer Format for Transmit Time-Stamp Insertion........................................................... 14-198
Transmit Frame Control Block ......................................................................................... 14-199
Example of eTSEC Memory Structure for BDs ............................................................... 14-201
Buffer Descriptor Ring...................................................................................................... 14-202
Transmit Buffer Descriptor ............................................................................................... 14-202
Mapping of TxBDs to a C Data Structure......................................................................... 14-203
Receive Buffer Descriptor................................................................................................. 14-205
Mapping of RxBDs to a C Data Structure ........................................................................ 14-206
DMA Block Diagram............................................................................................................ 15-1
DMA Operational Flow Chart .............................................................................................. 15-4
DMA Signal Summary.......................................................................................................... 15-4
DMA Mode Registers (MRn) ............................................................................................... 15-9
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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