MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 32

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
16.3.1.3.3
16.3.1.3.4
16.3.1.4
16.3.1.4.1
16.3.1.4.2
16.3.1.4.3
16.3.1.4.4
16.3.1.4.5
16.3.1.4.6
16.3.1.4.7
16.3.1.4.8
16.3.1.4.9
16.3.2
16.3.2.1
16.3.2.2
16.3.2.3
16.3.2.4
16.3.2.5
16.3.2.6
16.3.2.7
16.3.2.8
16.3.2.9
16.3.2.10
16.3.2.11
16.3.2.12
16.3.2.13
16.3.2.14
16.3.2.15
16.3.2.16
16.3.2.17
16.3.2.18
16.3.2.19
16.3.2.20
16.4
16.4.1
16.4.1.1
16.4.1.2
16.4.1.3
16.4.1.4
xxxii
Functional Description................................................................................................. 16-42
PCI Configuration Header ....................................................................................... 16-30
PCI Bus Arbitration ................................................................................................. 16-42
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI Error Management Registers........................................................................ 16-23
PCI Vendor ID Register—Offset 0x00 ................................................................ 16-30
PCI Device ID Register—Offset 0x02 ................................................................ 16-31
PCI Bus Command Register—Offset 0x04 ......................................................... 16-31
PCI Bus Status Register—Offset 0x06................................................................ 16-32
PCI Revision ID Register—Offset 0x08 ............................................................. 16-34
PCI Bus Programming Interface Register—Offset 0x09 .................................... 16-34
PCI Subclass Code Register—Offset 0x0A......................................................... 16-35
PCI Bus Base Class Code Register—Offset 0x0B .............................................. 16-35
PCI Bus Cache Line Size Register—Offset 0x0C............................................... 16-35
PCI Bus Latency Timer Register—0x0D ............................................................ 16-36
PCI Base Address Registers ................................................................................ 16-36
PCI Subsystem Vendor ID Register..................................................................... 16-38
PCI Subsystem ID Register ................................................................................. 16-39
PCI Bus Interrupt Line Register .......................................................................... 16-39
PCI Bus Interrupt Pin Register ............................................................................ 16-40
PCI Bus Minimum Grant Register (MIN_GNT)................................................. 16-40
PCI Bus Maximum Latency Register (MAX_LAT)............................................ 16-41
PCI Bus Function Register (PBFR) ..................................................................... 16-41
PCI Bus Arbiter Configuration Register (PBACR)............................................. 16-41
PCI Bus Arbiter Operation .................................................................................. 16-43
PCI Bus Parking .................................................................................................. 16-44
Broken Master Lock-Out ..................................................................................... 16-44
Power-Saving Modes and the PCI Arbiter .......................................................... 16-45
PCI Bus Capabilities Pointer Register ................................................................. 16-39
PCI Inbound Window Base Extended Address Registers
PCI Inbound Window Attributes Registers (PIWARn) ................................... 16-21
PCI Error Detect Register (ERR_DR)............................................................. 16-24
PCI Error Capture Disable Register (ERR_CAP_DR).................................... 16-25
PCI Error Enable Register (ERR_EN) ............................................................ 16-26
PCI Error Attributes Capture Register (ERR_ATTRIB) ................................. 16-27
PCI Error Address Capture Register (ERR_ADDR)....................................... 16-28
PCI Error Extended Address Capture Register
PCI Error Data Low Capture Register (ERR_DL) .......................................... 16-29
PCI Error Data High Capture Register (ERR_DH)......................................... 16-29
PCI Gasket Timer Register (GAS_TIMR) ...................................................... 16-29
(PIWBEARn) .............................................................................................. 16-21
(ERR_EXT_ADDR).................................................................................... 16-28
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