MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1209

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4.2
Both INTx and message signaled interrupts (MSI) are supported; however there are differences depending
on whether the PCI Express controller is configured as an RC or EP device.
17.4.2.1
17.4.2.1.1
Hardware INTx message generation is not supported in EP mode.
17.4.2.1.2
In EP mode, the PCI Express controller can be configured to automatically generate MSI transactions to
the root complex when an interrupt event occurs. The PCI Express controller uses irq_out (an internal
version of the IRQ_OUT signal) to trigger the generation of the MSI. To trigger the MSI, interrupt events
must be routed to irq_out by setting the EP (external pin) bit in the associated Interrupt Destination register
in the PIC. Note that the IRQ_OUT signal should not be used for any other function if it is being used to
trigger MSI transactions.
The remote root complex is expected set up the MSI capability structure of all endpoints at system
initialization by filling the Message Address and Message Data registers with appropriate values and
setting the MSIE bit in the MSI Message Control register.
With the PCI Express controller properly configured, when it detects the leading edge of irq_out going
active, it generates a PCI Express memory write transaction to the address specified in the MSI Message
Address register (and MSI Message Upper Address register) with a data payload as specified in the MSI
Message Data register (with leading zeros appended).
17.4.2.1.3
Software can generate outbound assert or deassert INTx message transactions by using the outbound
ATMU mechanism described in
17.4.2.1.4
Host software has to set up the MSI capability registers to enable MSI mode, and have the correct values
for the MSI address and data register. Then local software has to read the MSI address in the MSI
capability register and configure the outbound ATMU window to map the translated address to the MSI
address. Software has to determine the number of allocated messages in the MSI capability register and
Freescale Semiconductor
Transaction
Outbound
response
Type
Interrupts
EP Interrupt Generation
Hardware INTx Message Generation
Hardware MSI Generation
Software INTx Message Generation
Software MSI Generation
Internal platform response with
error (for example, an ECC error on
a DDR read or the transaction
maps to unknown address space).
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Error Type
Table 17-126. Error Conditions (continued)
Section 17.4.1.9.1, “Outbound ATMU Message
Send poisoned TLP (EP=1) completion(s) for data that are known bad.
If the poison data happens in the middle of the packet, the rest of the
response packet(s) is also poisoned.
Action
PCI Express Interface Controller
Generation.”
17-113