MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1311

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.4.18 DMA Control Register (DCR)
The DMA control register controls, shown in
to DMA operations.
20.5
The following sections provide a brief functional description of the major system blocks, including the
data buffer, DMA CCB interface, register bank, register bus interface, dual-port memory wrapper,
data/command controller, clock and reset manager, and clock generator.
Freescale Semiconductor
Offset: 0x40C (DCR)
Reset
Reset
RD_PF_SIZE
RD_SAFE
RD_PFE
SNOOP
W
W
26–28
R
R
Field
0–24
25
29
30
31
16
0
Functional Description
Reserved.
Snoop attribute.
0 DMA transactions are not snooped by the CPU data cache
1 DMA transactions are snooped by the CPU data cache
Reserved.
Read safe. This bit should be set only if the target of a read-DMA operation is a well-behaved memory that is
not affected by the read operation and returns the same data if read again from the same location. This means
that unaligned reading operation can be rounded up to enable more efficient read operations.
0 It is not safe to read more bytes that were intended
1 It is safe to read more bytes that were intended
Read prefetch enable. This bit should be set if the target of read-DMA operation is a well-behaved memory that
is not affected by the read operation and returns the same data if read again from the same location. This
means that prefetch of data can be done by the internal bus units and it results in faster read completion.
0
1
Read prefetch size. Determines the prefetch byte count to be used if RD_PFE is set.
0
1
It is not allowed to prefetch data on DMA read operation
It is allowed to prefetch data on DMA read operation
64 bytes prefetch
32 bytes prefetch
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Figure 20-20. DMA Control Register (DCR)
Table 20-26. DCR Field Descriptions
24
Figure
SNOOP
25
20-20, various settings that affect the system response
All zeros
All zeros
Description
—
26
28
RD_SAFE
Enhanced Secure Digital Host Controller
29
RD_PFE
30
Access: Read/Write
RD_PF_SIZE
15
31
20-37