MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1158

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.8.3.9
The memory base register is shown in
Table 17-64
17.3.8.3.10 PCI Express Memory Limit Register—0x22
The memory limit register is shown in
Table 17-65
17-62
Offset 0x22
Reset
15–4 Memory Base Specifies bits 31:20 of the non-prefetchable memory space start address. Typically used for specifying
Offset 0x20
Reset
Bits
15–4 Memory Limit Specifies bits 31:20 of the non-prefetchable memory space ending address. Typically used for
3–0
Bits
3–0
W
R
W
R
15
15
Name
Name
—
—
describes the memory base register fields.
describes the memory base register fields.
PCI Express Memory Base Register—0x20
memory-mapped I/O space.
Note: Inbound posted transactions hitting into the mem base/limit range are ignored; inbound
Reserved
specifying memory-mapped I/O space.
Note: Inbound posted transactions hitting into the mem base/limit range are ignored; inbound
Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 17-64. PCI Express Memory Base Register Field Description
Table 17-65. PCI Express Memory Limit Register Field Description
non-posted transactions hitting into the mem base/limit range results in an unsupported request
response.
non-posted transactions hitting into the mem base/limit range results in unsupported request
response.
Figure 17-66. PCI Express Memory Base Register
Figure 17-67. PCI Express Memory Limit Register
Memory Limit
Memory Base
Figure
Figure
17-66.
17-67.
All zeros
All zeros
Description
Description
4
4
3
3
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
—
—
0
0