MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 640

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DUART
12.4.4.2
A parity error occurs, and ULSR[PE] is set, when unexpected parity values are encountered while
receiving data. In FIFO mode, ULSR[PE] is set when the character with the error is at the top of the FIFO.
ULSR[PE] is cleared when ULSR is read or when a new character is loaded into the URBR.
12.4.4.3
When a new (overwriting character) STOP bit is detected and the old character is lost, an overrun error
occurs and ULSR[OE] is set. In FIFO mode, ULSR[OE] is set after the receiver FIFO is full (despite the
receiver FIFO trigger level setting) and a new character has been received into the internal receiver shift
register. Data in the FIFO is not overwritten; only the shift register data is overwritten. Therefore, the
interrupt occurs immediately. ULSR[OE] is cleared when ULSR is read.
12.4.5
The UARTs use an alternate mode (FIFO mode) to relieve the processor core from excessive software
overhead. The FIFO control register (UFCR) is used to enable and clear the receiver and transmitter FIFOs
and set the FIFO receiver trigger level UFCR[RTL] to control the received data available interrupt
UIER[ERDAI].
The UFCR also selects the type of DMA signaling. The UDSR[RXRDY] indicates the status of the
receiver FIFO. The DMA status registers (UDSR[TXRDY]) indicate when the transmitter FIFO is full.
When in FIFO mode, data written to UTHR is placed into the transmitter FIFO. The first byte written to
UTHR is the first byte onto the UART bus.
12.4.5.1
In FIFO mode, the UIER[ERDAI] is set when a time-out interrupt occurs. When a receive data time-out
occurs there is a maskable interrupt condition (through UIER[ERDAI]). See
Enable Register (UIER) (ULCR[DLAB] = 0),”
The interrupt ID register (UIIR) indicates if the FIFOs are enabled. Interrupt ID3 UIIR[IID3] bit is only
set for FIFO mode interrupts. The character time-out interrupt occurs when no characters have been
removed from or input to the receiver FIFO during the last four character times and there is at least one
character in the receiver FIFO during this time. The character time-out interrupt (controlled by
UIIR[IIDn]) is cleared when the URBR is read. See
(ULCR[DLAB] = 0),”
The UIIR[FE] bits indicate if FIFO mode is enabled.
12.4.5.2
The UDSR[RXRDY] bit reflects the status of the receiver FIFO or URBR. In mode 0 (UFCR[DMS] is
cleared), UDSR[RXRDY] is cleared when there is at least one character in the receiver FIFO or URBR
and it is set when there are no more characters in the receiver FIFO or URBR. This occurs regardless of
the setting of the UFCR[FEN] bit. In mode 1 (UFCR[DMS] and UFCR[FEN] are set), UDSR[RXRDY]
12-22
FIFO Mode
Parity Error
Overrun Error
FIFO Interrupts
DMA Mode Select
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
for more information.
for more details on interrupt enables.
Section 12.3.1.5, “Interrupt ID Registers (UIIRn)
Section 12.3.1.4, “Interrupt
Freescale Semiconductor