MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1535

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 23-35
Freescale Semiconductor
19–23
0–18
Bits
Name
EICA
describes the fields of SRDS2CR2.
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved
SATA receiver electrical idle detection control for lane A.
Settings for bits 19–21:
000 Loss of signal detect function is disabled.
001 Default SGMII levels (low = 30 mV, high = 100 mV)
010 Intermediate level (low = 38 mV, high = 120 mV)
011 Intermediate level (low = 50 mV, high = 150 mV)
100 SATA1 levels (low = 65 mV, high = 175 mV)
101 Default SATA2 levels (low = 75 mV, high = 200 mV)
110 Intermediate level (low = 88 mV, high = 225 mV)
111 Intermediate level (low = 100mV, high = 250 mV)
Recommended setting per protocol:
Settings for bits 22–23:
For SGMII:
00 Exit from Idle ~88UI and Unexpected Idle Detect ~1us (Application Mode)
01 Exit from Idle ~88UI and Unexpected Idle Detect ~10us
10 Exit from Idle ~48UI and Unexpected Idle Detect ~1us
11 Bypass
For SATA:
00 20 consecutive UI with no glitch (for exit from idle and for loss of signal detection).
01 40 consecutive UI with no glitch (for exit from idle and for loss of signal detection).
10 80 consecutive UI with no glitch (for exit from idle and for loss of signal detection).
11 20 consecutive UI with no glitch (for exit from idle and for loss of signal detection).
Recommended setting per protocol:
• SGMII: 001
• SATA: 101
• SGMII: 00
• SATA: 00
Table 23-35. SRDS2CR2 Field Descriptions
Description
Global Utilities
23-43