MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1256

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
19.3.4.8
PhyCtrlCfg1, shown in
Table 19-24
19-26
1 Reset value must be preserved when writing to the register.
31–13
Offset 0x1_815C
Reset
Reset 0
11–9
8–7
6–4
Bit
12
W
W
R
R
31
15
ENDEC_EN
0
FPRFTI
describes the PhyCtrlCfg1 fields.
Name
PHY Control Configuration Register1 (PhyCtrlCfg1)
—
—
—
—
13
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 19-24. PHY Control Configuration Register1 (PhyCtrlCfg1)
Figure
Reserved
enable 8B/10B encoding and decoding. When negated low, the PCS is configured to operate in
10-bit mode; the 8B/10B encoder/decoders are bypassed and it is assumed this is done
elsewhere.
Reserved. Reset value must be preserved when writing to the register.
Force PHY ready, force Tx idle. This pair of signals determines how phyRdy is driven, how the
output buffer IDLE condition is controlled and how disparity errors in ALIGN primitives should be
tolerated during OOB. The IDLE condition is defined in SATA as both traces of the transmit
differential pair being driven to common mode.
In this mode phyRdy and Tx buffer IDLE control driven by OOB state machine. Disparity errors in
ALIGN primitives are not tolerated during OOB.
In this mode phyRdy and Tx buffer IDLE control driven by OOB state machine.
Disparity errors in ALIGN primitives are tolerated during OOB.
In this mode phyRdy is asserted high and Tx buffer IDLE control is forced off, causing the output
buffer to be enabled. Tolerance of disparity errors in ALIGN primitives is of no consequence,
because OOB is bypassed.
In this mode phyRdy is asserted high and Tx buffer IDLE control is forced on, causing the output
buffer to the IDLE condition. Tolerance of disparity errors in ALIGN primitives is of no consequence
as OOB is bypassed.
Reserved
Encode decode enable. When asserted high, it enables the PCS to operate in 8 bit mode, and to
• frcPhyRdy = 0
• frcTxIdle = 0
• frcPhyRdy = 0
• frcTxIdle = 1
• frcPhyRdy = 1
• frcTxIdle = 0
• frcPhyRdy = 1
• frcTxIdle = 1
ENDEC_
EN
12
1
1
19-24, controls the configuration of the link layer.
Table 19-24. PhyCtrlCfg1 Field Descriptions
11
1
—
0
9
0
All zeros
—
FPRFTI
0
8
Description
0
7
0
6
—
0
0
4
0
3
Freescale Semiconductor
LPB_EN
0
Access: Read/Write
0
1
—
16
0
0