MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 621

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.2
The DUART signals are described in
prepended with the UART_ prefix as shown in the table, the functional (abbreviated) signal names are
often used throughout this chapter.
12.3
Table 12-2
the complete description of each register. Note that the full register address is comprised of CCSRBAR
together with the block base address and offset listed in
There are two complete sets of DUART registers (one for each UART). The two UARTs on the device are
identical, except that the registers for each UART are located at different offsets. Throughout this chapter,
the registers are described by a singular acronym: for example, LCR represents the line control register for
either UART0 or UART1.
The registers in each UART interface are used for configuration, control, and status. The divisor latch
access bit, ULCR[DLAB], is used to access the divisor latch least- and most-significant bit registers and
Freescale Semiconductor
UART_SOUT[0:1]
UART_CTS[0:1]
UART_RTS[0:1]
UART_SIN[0:1]
Signal
External Signal Descriptions
Memory Map/Register Definition
lists the DUART registers and their offsets. It lists the address, name, and a cross-reference to
I/O
O
O
I
I
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Serial data in. Data is received on the receivers of UART0 and UART1 through the respective serial
data input signal, with the least-significant bit received first.
Serial data out. The serial data output signals for the UART0 and UART1 are set ('mark' condition)
when the transmitter is disabled, idle, or operating in the local loopback mode. Data is shifted out on
these signals, with the least significant bit transmitted first.
Clear to send. These active-low inputs are the clear-to-send inputs. They are connected to the
respective RTS outputs of the other UART devices on the bus. They can be programmed to generate
an interrupt on change-of-state of the signal.
Request to send. UART_RTSx are active-low output signals that can be programmed to be
automatically negated and asserted by either the receiver or transmitter. When connected to the
clear-to-send (CTS) input of a transmitter, this signal can be used to control serial data flow.
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—An internal logic sample signal, rxcnt , uses the frequency of the
Timing Assertion/Negation— An internal logic sample signal, rxcnt , uses the frequency of the
Timing Assertion/Negation—Sampled at the rising edge of every platform clock.
Timing Assertion/Negation—Updated and driven at the rising edge of every platform clock.
Table 12-1. DUART Signals—Detailed Signal Descriptions
State
State
State
State
Asserted/Negated—Represents the data being received on the UART interface.
Asserted/Negated—Represents the data being transmitted on the respective UART
Asserted/Negated—Represent the clear to send condition for their respective UART.
Asserted/Negated—Represents the data being transmitted on the respective UART
baud-rate generator to sample the data on SIN.
interface.
baud-rate generator to update and drive the data on SOUT.
interface.
Table
12-1. Note that although the actual device signal names are
Table
Description
12-2.
DUART
12-3