MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 466

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
If the FETCH_FIFO_ENQ_COUNT field is 0x1111_1111, then adding another entry to the FIFO clears
the register and causes the FFE_CNT bit (if enabled) to be set in the controller’s interrupt status register
(see
10.4.3.1.2
The descriptor finished counter, shown in
successfully completed processing. It does not count descriptors that halt due to error.
When the DESCRIPTOR_FINISHED_COUNT field reaches 0x1111_1111, then the next completed
descriptor clears the counter and causes the DF_CNT bit (if enabled) to be set in the controller’s interrupt
status register (see
(IER, ISR,
10.4.3.1.3
The data bytes in counter, shown in
EU input FIFO. If other parcels such as context or ICV are placed in the input FIFO, they are not counted.
When a secondary EU is used, data going only to the secondary EU (such as a hash-only region or
authentication data) is counted, but the data used by both EUs is not double counted.
If
DI_CNT bit is set (see
(IER, ISR,
If this counter is read by software in 32-bit increments, then the least significant 32 bits must be read first,
followed by the most significant 32 bits. If this counter is written by software in 32 bit increments, then
the most significant 32 bits must be written first, followed by the least significant 32 bits. Note that 32 bit
reads and writes must not be interleaved (that is, read low, write low, read high, write high is not allowed).
These restrictions are required to maintain counter coherency.
10-36
Offset Channel 0x3_1500
Reset
Offset Channel 0x3_1508
Reset
this counter reaches all 1s
W
Section 10.5.4.2, “Interrupt Enable, Interrupt Status, and Interrupt Clear Registers (IER, ISR,
W
R
R
0
0
ICR)”).
ICR)”).
Descriptor Finished Counter
Data Bytes In Counter
Section 10.5.4.2, “Interrupt Enable, Interrupt Status, and Interrupt Clear Registers
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 10.5.4.2, “Interrupt Enable, Interrupt Status, and Interrupt Clear Registers
—
—
, at the next count it rolls over to all 0s and the interrupt enable register’s
Figure 10-7. Fetch FIFO Enqueue Counter
Figure 10-8. Descriptor Finished Counter
Figure
Figure
10-9, indicates the total number of bytes written into a primary
10-8, indicates the total number of descriptors that have
All zeros
All zeros
31 32
31 32
Descriptor_Finished_Count
Fetch_FIFO_ENQ_COUNT
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
ICR)”).
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