MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 71

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure
Number
16-59
16-60
16-61
16-62
16-63
16-64
16-65
17-1
17-2
17-3
17-4
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17-6
17-7
17-8
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17-10
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17-20
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17-22
17-23
17-24
17-25
17-26
17-27
17-28
17-29
17-30
Freescale Semiconductor
PCI Type 0 Configuration Translation ................................................................................ 16-62
PCI Parity Operation........................................................................................................... 16-65
Address Invariant Byte Ordering—4 bytes Outbound........................................................ 16-69
Address Invariant Byte Ordering—4 bytes Inbound .......................................................... 16-69
Address Invariant Byte Ordering—8 bytes Outbound........................................................ 16-70
Address Invariant Byte Ordering—2 bytes Inbound .......................................................... 16-70
CFG_DATA Byte Ordering................................................................................................. 16-70
PCI Express Controller Block Diagram................................................................................ 17-2
PCI Express Configuration Address Register (PEX_CONFIG_ADDR) ........................... 17-10
PCI Express Configuration Data Register (PEX_CONFIG_DATA) .................................. 17-11
PCI Express Outbound Completion Timeout Register (PEX_OTB_CPL_TOR)............... 17-11
PCI Express Configuration Retry Timeout Register (PEX_CONF_RTY_TOR) ............... 17-12
PCI Express Configuration Register (PEX_CONFIG) ....................................................... 17-12
PCI Express PME and Message Detect Register (PEX_PME_MES_DR)......................... 17-13
PCI Express PME and Message Disable Register (PEX_PME_MES_DISR) ................... 17-15
PCI Express PME and Message Interrupt Enable Register (PEX_PME_MES_IER) ........ 17-17
PCI Express Power Management Command Register (PEX_PMCR) ............................... 17-18
IP Block Revision Register 1 .............................................................................................. 17-19
IP Block Revision Register 2 .............................................................................................. 17-19
RC Outbound Transaction Flow ......................................................................................... 17-20
PCI Express Outbound Translation Address Registers (PEXOTARn) ............................... 17-21
PCI Express Outbound Translation Extended Address Registers (PEXOTEARn) ............ 17-21
PCI Express Outbound Window Base Address Registers (PEXOWBARn) ...................... 17-22
PCI Express Outbound Window Attributes Register 0 (PEXOWAR0).............................. 17-22
PCI Express Outbound Window Attributes Registers 1–4 (PEXOWARn) ........................ 17-23
RC Inbound Transaction Flow ............................................................................................ 17-26
PCI Express Inbound Translation Address Registers (PEXITARn) ................................... 17-26
PCI Express Inbound Window Base Address Registers (PEXIWBARn)........................... 17-27
PCI Express Inbound Window Base Extended Address Registers (PEXIWBEARn) ........ 17-27
PCI Express Inbound Window Attributes Registers (PEXIWARn).................................... 17-28
PCI Express Error Detect Register (PEX_ERR_DR) ......................................................... 17-30
PCI Express Error Interrupt Enable Register (PEX_ERR_EN).......................................... 17-32
PCI Express Error Disable Register (PEX_ERR_DISR).................................................... 17-34
PCI Express Error Capture Status Register (PEX_ERR_CAP_STAT)............................... 17-36
PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)
PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0)
PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)
Internal Source, Outbound Transaction.......................................................................... 17-37
External Source, Inbound Transaction ........................................................................... 17-37
Internal Source, Outbound Transaction.......................................................................... 17-38
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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