MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 353

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-55
8.5.8
The DDR memory controller supports auto-refresh and self-refresh. Auto refresh is used during normal
operation and is controlled by the DDR_SDRAM_INTERVAL[REFINT] value; self-refresh is used only
when the DDR memory controller is set to enter a sleep power management state. The REFINT value,
which represents the number of memory bus clock cycles between refresh cycles, must allow for possible
outstanding transactions to complete before a refresh request is sent to the memory after the REFINT value
is reached. If a memory transaction is in progress when the refresh interval is reached, the refresh cycle
waits for the transaction to complete. In the worst case, the refresh cycle must wait the number of bus clock
cycles required by the longest programmed access. To ensure that the latency caused by a memory
transaction does not violate the device refresh period, it is recommended that the programmed value of
REFINT be less than that required by the SDRAM.
When a refresh cycle is required, the DDR memory controller does the following:
Freescale Semiconductor
1. Completes all current memory requests.
2. Closes all open pages with a PRECHARGE-ALL command to each DDR SDRAM bank with an
3. Issues one or more auto-refresh commands to each DDR SDRAM bank (as identified by its chip
open page (as indicated by the row open table).
select) to refresh one row in each logical bank of the selected physical bank.
SDRAM Clock
DDR SDRAM Refresh
shows the use of the WR_DATA_DELAY parameter.
MDM n
MDQS
MDM n
MDQS
MRAS
MCAS
MDQ n
MDQ n
MWE
MCS
MA n
Figure 8-55. Write Timing Adjustments Example for Write Latency = 1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
ROW
0
1
ACTTORW
2
3
COL
4
D0
D0
5
D1 D2 D3
D1 D2 D3
COL
6
00
00
D0
D0
7
D1 D2
D1 D2
8
D3
D3
9
10
11
DDR Memory Controller
12
1/4 Delay
1/2 Delay
8-79