MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 533

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Interrupt status register bits can be set by writes from the host, but only if the corresponding bit is cleared
in the interrupt mask register. Bits masked by the interrupt mask register bits are always zero.
The CRCU interrupt status and interrupt mask registers can be cleared by programming the CRCU reset
control register, as described in
Offset 0x3_F030
Freescale Semiconductor
Reset
W
R
0–48
Bits
0
49
50
51
52
53
54
55
Name
ERE
DSE
KSE
ICE
PE
CE
—
IE
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-44. CRCU Interrupt Status Register Bit Definitions
—
Reserved
Integrity Check (CRC) Error:
0 No error detected
1 Integrity check error detected. An ICV (CRC) check was performed and the supplied
Polynomial Error.
0 No error.
1 An invalid polynomial has been written to the Key or Control Register.
Internal Error. Indicates the CRCU has been locked up and requires a reset before use.
0 No internal error detected
1 Internal error detected
Note: This bit is asserted any time an enabled error condition occurs and can only be
Early Read Error. The CRCU context was read before the CRCU completed the
requested operation.
0 No error detected
1 Early read error
Context Error. The CRCU mode, key size, control, context, or key register was modified
1 Context error
Key Size Error. A value other than 0 or 4 has been written to the CRCU key size
register.
0 No error detected
1 Key size error
Data Size Error. An non-byte-multiple size has been written to the CRCU data size
register.
0 No error detected
1 Data size error
Figure 10-46. CRCU Interrupt Status Register
0 No error detected
Section 10.7.3.5, “CRCU Reset Control
ICV (CRC) did not match the one computed by the CRCU.
after processing had begun.
cleared by resetting the CRCU.
48
ICE PE IE ERE CE KSE DSE ME AE
49
All zeros
50 51
Description
52
53
54
Register.”
55
56
57 58 59 60
Security Engine (SEC) 3.0
—
Access: Read/Write
IFO
61
62
10-103
—
63