MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 285

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
0x140–
0x150–
0x168–
0x0CC
Offset
0x08C
0x0C0
0x0C4
0x0C8
0x10C
0x11C
0x14C
0x17C
0x010
0x018
0x080
0x084
0x088
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x130
0x144
0x148
0x15F
0x160
0x164
0x16F
0x170
0x174
0x178
0x180
0x184
CS2_BNDS—Chip select 2 memory bounds
CS3_BNDS—Chip select 3 memory bounds
CS0_CONFIG—Chip select 0 configuration
CS1_CONFIG—Chip select 1 configuration
CS2_CONFIG—Chip select 2 configuration
CS3_CONFIG—Chip select 3 configuration
CS0_CONFIG_2—Chip select 0 configuration 2
CS1_CONFIG_2—Chip select 1 configuration 2
CS2_CONFIG_2—Chip select 2 configuration 2
CS3_CONFIG_2—Chip select 3 configuration 2
TIMING_CFG_3—DDR SDRAM timing configuration 3
TIMING_CFG_0—DDR SDRAM timing configuration 0
TIMING_CFG_1—DDR SDRAM timing configuration 1
TIMING_CFG_2—DDR SDRAM timing configuration 2
DDR_SDRAM_CFG—DDR SDRAM control configuration
DDR_SDRAM_CFG_2—DDR SDRAM control configuration 2
DDR_SDRAM_MODE—DDR SDRAM mode configuration
DDR_SDRAM_MODE_2—DDR SDRAM mode configuration 2
DDR_SDRAM_MD_CNTL—DDR SDRAM mode control
DDR_SDRAM_INTERVAL—DDR SDRAM interval configuration
DDR_DATA_INIT—DDR SDRAM data initialization
DDR_SDRAM_CLK_CNTL—DDR SDRAM clock control
Reserved
DDR_INIT_ADDR—DDR training initialization address
DDR_INIT_EXT_ADDR—DDR training initialization extended address
Reserved
TIMING_CFG_4— DDR SDRAM timing configuration 4
TIMING_CFG_5— DDR SDRAM timing configuration 5
Reserved
DDR_ZQ_CNTL— DDR ZQ calibration control
DDR_WRLVL_CNTL— DDR write leveling control
Reserved
DDR_SR_CNTR — DDR Self Refresh Counter
DDR_SDRAM_RCW_1 — DDR Register Control Words 1
DDR_SDRAM_RCW_2 — DDR Register Control Words 2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-5. DDR Memory Controller Memory Map (continued)
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0011_0105
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0200_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0200_0000
0x0000_0000
0x0000_0000
Reset
—
—
—
—
DDR Memory Controller
Section/Page
8.4.1.10/8-29
8.4.1.11/8-29
8.4.1.12/8-30
8.4.1.13/8-33
8.4.1.14/8-33
8.4.1.15/8-34
8.4.1.16/8-34
8.4.1.17/8-35
8.4.1.18/8-36
8.4.1.19/8-37
8.4.1.20/8-39
8.4.1.21/8-40
8.4.1.22/8-43
8.4.1.23/8-44
8.4.1.24/8-45
8.4.1.1/8-12
8.4.1.1/8-12
8.4.1.2/8-13
8.4.1.2/8-13
8.4.1.2/8-13
8.4.1.2/8-13
8.4.1.3/8-15
8.4.1.3/8-15
8.4.1.3/8-15
8.4.1.3/8-15
8.4.1.4/8-16
8.4.1.5/8-17
8.4.1.6/8-19
8.4.1.7/8-21
8.4.1.8/8-23
8.4.1.9/8-26
—
—
—
—
8-11