MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1136

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
Table 17-31
in PEX_ERR_CAP_R0 (see
transaction.
17.3.6.7
Together with the other PCI Express error capture registers, PEX_ERR_CAP_R2 allows vital error
information to be captured when an error occurs. Different error information is reported depending on
whether the error source is from an outbound transaction from an internal source or from an inbound
transaction from an external source; the source of the captured error is reflected in
PEX_ERR_CAP_STAT[GSID]. Note that after the initial error is captured, no further capturing is
performed until the PEX_ERR_CAP_STAT[ECV] bit is clear.
17.3.6.7.1
PEX_ERR_CAP_R2 for the case when the error is caused by an outbound transaction from an internal
source (that is, PEX_ERR_CAP_STAT[GSID]
Table 17-32
outbound transaction from an internal source.
17-40
Offset 0xE30
Reset
W
R
0
0–31
0–31
Bits
Bit
describes the fields of PEX_ERR_CAP_R1 for the case when the FMT and TYPE subfields
describes the fields of PEX_ERR_CAP_R2 for the case when the error is caused by an
PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)
PEX_ERR_CAP_R2—Outbound Case
Figure 17-32. PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2)
Table 17-31. PCI Express Error Capture Register 1 Field Descriptions
Table 17-32. PCI Express Error Capture Register 2 Field Descriptions
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
Name
GH1
OD1
External Source, Inbound Memory Request Transaction
PEX second DW (4-byte) header. This field contains the second DW (4-byte) of the
captured PCI Express packet header.
24–31
16–23
8–15
4–7
0–3
Internal platform transaction information. Reserved for factory debug.
Table
Internal Source, Outbound Transaction
Internal Source, Outbound Transaction
17-28) indicate the error was caused by an inbound memory request
Requester ID[15:8]
Requester ID[7:0]
Tag[7:0]
First DW BE[3:0]
Last DW BE[3:0]
0h02), is shown in
All zeros
OD1
Description
Description
Figure
17-32.
Freescale Semiconductor
Access: Read/Write
31