MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1239

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 19-7
19.3.2.7
HStatus, shown in
When an event occurs, the interrupt bit is set regardless of the status of the associated interrupt enable bit.
The interrupt signal from the SATA controller is gated with the associated interrupt enable register. For all
interrupt bits other than the interrupt on command complete bit, when software has processed the interrupt
condition, it acknowledges the interrupt by writing a 1 to the interrupt source bit. This action will clear the
interrupt signal if there are no other outstanding interrupts in HStatus.
The interrupt on command complete requires special processing. This bit is set as a result of the
programmed interrupt coalescing algorithm running on the register CCR contents. For the interrupt on
command complete bit, the command(s) that have completed to cause this interrupt need to be cleared by
clearing the command N completed bit of the CCR. When the number or staleness of the CCR falls below
the programmed interrupt coalescing algorithm, the interrupt on command complete bit clears.
Table 19-8
Freescale Semiconductor
Offset 0x1_8028
Reset
Reset
Bit
31
30
W
W
R
R
HS_ON HS_OFF
31
15
0
describes the CHBA fields.
describes the HStatus fields.
HS_OFF
HS_ON
Host Status Register (HStatus)
Name
—
Figure
30
14
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Online/offline. This bit indicates if the SATA controller is online or offline.
0 Offline. The SATA controller is non-operational and the PHY is held in reset.
1 Online. The SATA controller is operational.
Going offline. This bit indicates that the SATA controller is going offline it is waiting for the
commands queued within the SATA controller or active at the device to complete.
0 Host is not in process going offline
1 Host is in process going offline
31–2
1–0
Bit
DUE
19-8, holds the status of the SATA controller as well as the interrupt sources.
BE
29
13
1
Figure 19-8. Host Status Register (HStatus)
DOE
28
12
0
Table 19-8. HStatus Field Descriptions
Table 19-7. CHBA Field Descriptions
CHBA
Name
—
CET
11
0
CER
10
0
Command header base address
Reserved, should be cleared.
FOT
0
9
All zeros
FOR
—
0
8
Description
Description
0
7
—
0
6
FE PR SIGU SNTFU
0
5
0
4
19
0
3
ME
18
0
2
DE
17
SATA Controller
0
1
Access: w1c
—
CC
16
0
0
19-9