MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 962

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14-214
Set up the MII Mgmt for a write cycle to the external PHY Mode control register to set up the interface mode selection,
Other information about the link is also returned.(Extend Status, No pre, Remote Fault, An Ability, Link status, extend
Set up the MII Mgmt for a write cycle to the external PHY Extended PHY control register #1 to set up the interface
Set up the MII Mgmt for a read cycle to PHY MII Mgmt register (write the PHY address and Register address),
If auto-negotiation was enabled in the PHY, check to see if PHY has completed Auto-Negotiation.
The PHY Status register is at address 0x1 and in this case the PHY Address is 0x00
(Uses the PHY address (0) and Register address (1) placed in MIIMADD register),
Write to MII Mgmt Control with 16-bit data intended for the external PHY register,
Write to MII Mgmt Control with 16-bit data intended for the external PHY register,
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-176. GMII Mode Register Initialization Steps (continued)
Read the MIIMSTAT register and check bit 10 (AN Done and Link is up),
MACnADDR1/2[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0100]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_000u_00u1_0100_0000]
MIIMADD[0000_0000_0000_0000_0000_0000_0001_0111]
MIIMADD[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMADD[0000_0000_0000_0000_0000_0000_0000_0001]
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
Check auto-negotiation attributes in the PHY as necessary.
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
where u is user defined based on desired configuration.
Perform an MII Mgmt write cycle to the external PHY.
Perform an MII Mgmt write cycle to the external PHY.
Perform an MII Mgmt read cycle of Status Register.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete.
Initialize MACnADDR1/2 (Optional)
Clear MIIMCOM[Read Cycle].
Initialize GADDR n (Optional)
Set MIIMCOM[Read Cycle].
Initialize RCTRL (Optional)
When MIIMIND[BUSY]=0,
Initialize IMASK (Optional)
Clear IEVENT register,
mode selection
Ability)
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