MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1134

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.6.6
Together with the other PCI Express error capture registers, PEX_ERR_CAP_R1 allows vital error
information to be captured when an error occurs. Different error information is reported depending on
whether the error source is from an outbound transaction from an internal source or from an inbound
transaction from an external source; the source of the captured error is reflected in
PEX_ERR_CAP_STAT[GSID]. Note that after the initial error is captured, no further capturing is
performed until the PEX_ERR_CAP_STAT[ECV] bit is clear.
17.3.6.6.1
PEX_ERR_CAP_R1 for the case when the error is caused by an outbound transaction from an internal
source (that is, PEX_ERR_CAP_STAT[GSID]
Table 17-29
outbound transaction from an internal source.
17-38
Offset 0xE2C
Reset
W
R
0
0–31
Bits
describes the fields of PEX_ERR_CAP_R1 for the case when the error is caused by an
PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)
PEX_ERR_CAP_R1—Outbound Case
Figure 17-30. PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)
Table 17-28. PCI Express Error Capture Register 0 Field Descriptions
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Name
GH0
PCI Express first DW (4-byte) header. This field contains the first DW (4-byte) of the
captured PCI Express packet header.
27–31
25–26
20–24
17–19
16
14–15
12–13
10–11
9
8
0–7
Internal Source, Outbound Transaction
External Source, Inbound Transaction
TYPE
FMT
Reserved
TC
Reserved
LENGTH[9:8]
Reserved
ATTR
EP
TD
LENGTH[7:0]
—
0h02), is shown in
All zeros
Description
Figure
17-30.
23 24
Freescale Semiconductor
Access: Read/Write
OD0
31