MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1212

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
In RC mode, the WAKE signal from the EP device can be connected to one of the external interrupt inputs
to service the WAKE request.
17.4.5
When a hot reset condition occurs, the controller (in both RC and EP mode) initiates a clean-up of all
outstanding transactions and returns to an idle state. All configuration register bits that are non-sticky are
reset. Link training takes place subsequently. The device is permitted to generate a hot reset condition on
the bus when it is configured as an RC device by setting the “Secondary Bus Reset” bit in the Bridge
Control Register in the configuration space. As an EP device, it is not permitted to generate a hot reset
condition; it can only detected a hot reset condition and initiates the clean-up procedure appropriately.
17.4.6
Typically, a link down condition occurs after a hot reset event; however, it is possible for the link to go
down unexpectedly without a hot reset event. When this occurs, a link down condition is detected
(PEX_PME_MSG_DR[LDD]=1). Link down is treated similarly to a hot reset condition.
Subsequently, while the link is down, all new posted outbound transactions are discarded. All new
non-posted ATMU transactions are errored out. Non-posted configuration transactions issued using
PEX_CONFIG_ADDR/PEX_CONFIG_DATA toward the link returns 0xFFFF_FFFF (all 1s). As soon as
the link is up again, the sending of transaction resumes.
Note that in EP mode, a link down condition causes the controller to reset all non-sticky bits in its PCI
Express configuration registers as if it had been hot reset.
17.5
17.5.1
In normal boot mode (cfg_cpu_boot = 1), the core is allowed to boot and configure the device. During this
time, the PCI Express interface retries all inbound PCI Express configuration transactions. When the core
has configured the device to a state where it can accept inbound PCI Express configuration transactions,
the boot code should set the CFG_READY bit in the PEX_CFG_READY register after which inbound
17-116
Initialization/Application Information
Hot Reset
Link Down
Boot Mode and Inbound Configuration Transactions
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI Express controller
in EP mode
Figure 17-132. WAKE Generation Example
GPOUT n
WAKE
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