MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1411

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
If software removes the queue head with the H-bit set, it must select another queue head still linked into
the schedule and set its H-bit. This should be completed before removing the queue head. The requirement
is that software keep one queue head in the asynchronous schedule, with its H-bit set. At the point software
has removed one or more queue heads from the asynchronous schedule, it is unknown whether the host
controller has a cached pointer to them. Similarly, it is unknown how long the host controller might retain
the cached information, as it is implementation dependent and may be affected by the actual dynamics of
the schedule load. Therefore, once software has removed a queue head from the asynchronous list, it must
retain the coherency of the queue head (link pointers). It cannot disturb the removed queue heads until it
knows that the host controller does not have a local copy of a pointer to any of the removed data structures.
The method software uses to determine when it is safe to modify a removed queue head is to handshake
with the host controller. The handshake mechanism allows software to remove items from the
asynchronous schedule, then execute a simple, lightweight handshake that is used by software as a key that
it can free (or reuse) the memory associated the data structures it has removed from the asynchronous
schedule.
The handshake is implemented with three bits in the host controller. The first bit is a command bit
(USBCMD[IAA]—interrupt on async advance doorbell) that allows software to inform the host controller
that something has been removed from its asynchronous schedule. The second bit is a status bit
(USBSTS[AAI]—interrupt on async advance) that the host controller sets after it has released all on-chip
state that may potentially reference one of the data structures just removed. When the host controller sets
this status bit, it also clears the command bit. The third bit is an interrupt enable
(USBINTR[AAE]—interrupt on async advance enable) that is matched with the status bit. If the status bit
is set and the interrupt enable bit is set, then the host controller asserts a hardware interrupt.
Figure 21-48
illustrates a general example where consecutive queue heads (B and C) are unlinked from
the schedule using the algorithm above. Before the unlink operation, the host controller has a copy of
queue head A.
The unlink algorithm requires that as software unlinks each queue head, the unlinked queue head is loaded
with the address of a queue head that will remain in the asynchronous schedule.
When the host controller observes that doorbell bit being set, it makes a note of the local reachable
schedule information. In this example, the local reachable schedule information includes both queue heads
(A & B). It is sufficient that the host controller can set the status bit (and clear the doorbell bit) as soon as
it has traversed beyond current reachable schedule information (that is, traversed beyond queue head (B)
in this example).
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor
21-77