MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 277

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2.1
The DDR memory controller supports the following modes:
8.3
This section provides descriptions of the DDR memory controller’s external signals. It describes each
signal’s behavior when the signal is asserted or negated and when the signal is an input or an output.
8.3.1
Memory controller signals are grouped as follows:
Freescale Semiconductor
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Support for double-bit error detection and single-bit error correction ECC (8-bit check word across
64-bit data)
Support for address parity for registered DIMMs
Open page management (dedicated entry for each logical bank)
Automatic DRAM initialization sequence or software-controlled initialization sequence
Automatic DRAM data initialization
Write leveling supported for DDR3 memories
Support for up to eight posted refreshes
Memory controller clock frequency of two or four times the SDRAM clock with support for sleep
power management
Support for error injection
Dynamic power management mode. The DDR memory controller can reduce power consumption
by negating the SDRAM CKE signal when no transactions are pending to the SDRAM.
Auto-precharge mode. Clearing DDR_SDRAM_INTERVAL[BSTOPRE] causes the memory
controller to issue an auto-precharge command with every read or write transaction.
Auto-precharge mode can be enabled for separate chip selects by setting
CSn_CONFIG[AP_n_EN].
Memory interface signals
Clock signals
Debug signals
External Signal Descriptions
Modes of Operation
Signals Overview
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
DDR Memory Controller
8-3