MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 491

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.1.3
The AESU key size register, shown in
24, or 32). Any key data beyond the number of bytes specified in the key size register is ignored. This
register is cleared when the AESU is reset or re-initialized. If a key size other than 16, 24, or 32 bytes (or
other than 16 bytes, in XCBC-MAC cipher mode) is specified, an illegal key size error is generated. If the
key size register is modified during processing, a context error is generated.
10.7.1.4
The AESU data size register, shown in
plaintext/ciphertext to be processed in the current descriptor. The number of data size register bits used by
the SEC, and the acceptable values for these bits, vary depending on the AES cipher mode selected as
specified in
Writing to this register signals the AESU to start processing data from the input FIFO as soon as it is
available. If the value of data size is modified during processing, a context error is generated. The register
is cleared when the AESU is reset or re-initialized.
Freescale Semiconductor
Offset 0x3_4008
Reset
Offset 0x3_4010
Reset
W
R
W
R
0
0
Table
AESU Key Size Register
AESU Data Size Register
10-24.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
1
SRT is not a new AES cipher mode, it is an AESU method of performing
AES counter mode with reduced context loading overhead specifically for
performing SRTP. It should be used with descriptor type 0010_1 ’srtp’ (but
may also be used with descriptor type 0010_0 for IPsec with AES counter
mode). See the section on “Context for SRT Cipher Mode” for more
information on how SRT cipher mode reduces context loading overhead.
GCM with ICV
CCM with ICV
Cipher Mode
Reserved
Table 10-23. AES Cipher Modes (continued)
XOR
Figure 10-23. AESU Data Size Register
Figure 10-22. AESU Key Size Register
Figure
Figure
—
—
10-22, is used to specify the number of bytes in the key (16,
10-23, is used to specify the number of bits (not bytes) of
ECM (56:57)
11
11
11
All zeros
All zeros
AUX2 (58)
all others
X
X
X
CM (61:62)
44 45
00
01
11
51 52
Security Engine (SEC) 3.0
Data Size
Access: Read/Write
Access: Read/Write
Key Size
10-61
63
63