MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1438

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.6.12.3.3 Split Transaction Execution State Machine for Isochronous
In this section, all references to micro-frame are in the context of a micro-frame within an H-Frame.
If the Active bit in the Status byte is a zero, the host controller ignores the siTD and continues traversing
the periodic schedule. Otherwise the host controller processes the siTD as specified below. A split
transaction state machine is used to manage the split-transaction protocol sequence. The host controller
uses the fields defined in
Transfers,”
State Machine for Interrupt,”
illustrates the state machine for managing an siTD through an isochronous split transaction. Bold, dotted
circles denote the state of the Active bit in the Status field of a siTD. The Bold, dotted arcs denote the
transitions between these states. Solid circles denote the states of the split transaction state machine and
the solid arcs denote the transitions between these states. Dotted arcs and boxes reference actions that take
place either as a result of a transition or from being in a state.
21.6.12.3.4 Periodic Isochronous—Do-Start-Split
Isochronous split transaction OUTs use only this state. An siTD for a split-transaction isochronous IN is
either initialized to this state, or the siTD transitions to this state from Do Complete Split when a case 2a
(IN) or 2b scheduling boundary isochronous split-transaction completes.
Each time the host controller reaches an active siTD in this state, it checks the siTD[S-mask] against
cMicroFrameBit. If there is a one in the appropriate position, the siTD executes a start-split transaction.
21-104
Active = 0
Transaction
plus the variable cMicroFrameBit defined in
Complete
IN Split
Transaction
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
OUT Split
Complete
Figure 21-58. Split Transaction State Machine for Isochronous
Advance Data
Buffer State
Active
Not
Section 21.6.12.3.2, “Tracking Split Transaction Progress for Isochronous
Active = 0
to track the progress of an isochronous split transaction.
Case 2(a,b)
Complete
siTD x–1
MDATA
Active = 1
Complete-
Active
Start-
Split
Split
Do
Do
siTD.S-Mask & cMicroFrameBit
Direction .eq. OUT
Not Last
Section 21.6.12.2.5, “Split Transaction Execution
NYET
CheckPreviousBit(C-prog-mask,
.and.
.and.
C-Mask, cMicroFrameBit)
Issue Start-Split
Transaction
Issue Complete-Split
siTD.S-Mask & cMicroFrameBit
Transaction
Direction .eq. IN
.and.
Freescale Semiconductor
Figure 21-58