MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 414

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset IIDR0–70x0210, 0x0230, 0x0250, 0x0270, 0x0290, 0x02B0, 0x02D0, 0x02F0
Reset 0
Programmable Interrupt Controller (PIC)
Table 9-40
9.3.7.4
The IIDRs, shown in
the internal interrupt sources listed in
is undefined.
9-44
12–15 PRIORITY Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level
16–31 VECTOR Vector (Affects only interrupts routed to int ). Contains the value returned when IACK is read and this interrupt
9–11
Bits
2–7
W
0
1
8
R
IIDR8–15 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03B0, 0x03D0, 0x03F0
IIDR16–23 0x0410, 0x0430, 0x0450, 0x0470, 0x0490, 0x04B0, 0x04D0, 0x04F0
IIDR24–31 0x0510, 0x0530, 0x0550, 0x0570, 0x0590, 0x05B0, 0x05D0, 0x05F0
IIDR32–39 0x0610, 0x0630, 0x0650, 0x0670, 0x0690, 0x06B0, 0x06D0, 0x06F0
IIDR40–47 0x0710, 0x0730, 0x0750, 0x0770, 0x0590, 0x07B0, 0x07D0, 0x07F0
IIDR48–53 0x0810, 0x0830, 0x0850, 0x0870, 0x0890, 0x08B0, 0x08D0, 0x08F0
IIDR54–63 0x0910, 0x0930, 0x0950, 0x0970, 0x0990, 0x09B0, 0x09D0, 0x09F0
1
EP CI0 CI1
0
Reserved in single-processor implementations.
Name
MSK
1
0
—
—
A
P
describes the IIVPR fields.
Internal Interrupt Destination Registers (IIDR n )
0
2
1
Mask. Mask interrupts from this source. MSK affects only interrupts routed to int .
0 An interrupt request is generated if the corresponding IPR bit is set.
1 Further interrupts from this source are disabled.
Activity. Indicates an interrupt has been requested or is in service. The VECTOR and PRIORITY values
should not be changed while this bit is set. Affects only interrupts routed to int .
0 No current interrupt activity associated with this source.
1 The interrupt field for this source is set in the IPR or ISR.
Reserved, should be cleared.
Polarity. Specifies the polarity for the internal interrupt. Note: Because all internal interrupts are active-high,
clearing this bit disables the interrupt.
0 Interrupt polarity is active-low. This value disables the interrupt.
1 Interrupt polarity is active-high.
Reserved, should be cleared.
of 0 inhibits signalling of this interrupt to the core. Affects only interrupts routed to int .
resides in the corresponding interrupt request register (IRR) for that core, as shown in
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
Figure
Figure 9-41. Internal Interrupt Destination Registers (IIDRs)
0
0
9-41, have the same fields and format as EIVDRs, except that they apply to
0
0
Table 9-40. IIVPR n Field Descriptions
0
Table
0
9-3. Only one destination bit may be set; otherwise, behavior
0
0
0
0
Description
0
—
0
0
0
0
0 0 0 0 0 0 0 0 0 0
Freescale Semiconductor
Figure
9-50.
Read/Write
29
Access:
P1
30
0
1
P0
31
1