MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 725

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
26–27
Bits
25
28
29
30
Name
EXEN
TODT
AMX
UTA
NA
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(EXS). When an internal bus monitor time-out exception is recognized and EXEN in the RAM
word is set, the UPM branches to the special exception start address (EXS) and begins
operating as the pattern defined there specifies.
The user should provide an exception pattern to negate signals controlled by the UPM in a
controlled fashion. For DRAM control, a handler should negate RAS and CAS to prevent data
corruption. If EXEN = 0, exceptions are ignored by UPM (but not by local bus) and execution
continues. After the UPM branches to the exception start address, it continues reading until the
LAST bit is set in the RAM word.
0 The UPM continues executing the remaining RAM words, ignoring any internal bus monitor
1 The current RAM word allows a branch to the exception pattern after the current cycle if an
Address multiplexing. Determines the source of LAD during an LALE phase. Any change in the
AMX field initiates a new LALE (address) phase.
00 LAD (and/or in conjunction with LA) is the non-multiplexed address. For example, column
01 Reserved
10 LAD (and/or in conjunction with LA) is driven with the multiplexed address according to
11 LAD (and/or in conjunction with LA) is driven with the contents of MAR. Used, for example,
Note: AMX must not change values in any RAM word which begins a loop.
Note: Source ID debug mode is only supported for the AMX = 00 setting.
0 The address increment function is disabled.
1 The address is incremented in the next cycle. In conjunction with the BR n [PS], the increment
UPM transfer acknowledge. Indicates assertion of transfer acknowledge in the current cycle.
0 Transfer acknowledge is not asserted in the current cycle.
1 Transfer acknowledge is asserted in the current cycle.
In case of UPM writes, program UTA and LAST in same RAM word.
In case of UPM reads, program UTA and LAST in consecutive or same RAM words.
be guaranteed between two successive accesses to the same memory bank. This feature is
critical when DRAM requires a RAS precharge time. TODT turns the timer on to prevent another
UPM access to the same bank until the timer expires.The disable timer period is determined in
M x MR[DS n ]. The disable timer does not affect memory accesses to different banks. Note that
TODT must be set together with LAST, otherwise it is ignored.
0 The disable timer is turned off.
1 The disable timer for the current bank is activated preventing a new access to the same bank
Exception enable. Allows branching to an exception pattern at the exception start address
Next burst address. Determines when the address is incremented during a burst access.
Turn-on disable timer. The disable timer associated with each UPM allows a minimum time to
time-out.
exception condition is detected.
value of LA n is 1, 2, or 4 for port sizes of 8 bits, 16 bits, and 32 bits, respectively.
(when controlled by the UPMs) until the disable timer expires. For example, precharge time.
Table 13-40. RAM Word Field Descriptions (continued)
address.
M x MR[AM]. For example, row address. See
(AMX)” for more information.
to initialize a mode.
Description
Section 13.4.4.4.7, “Address Multiplexing
Enhanced Local Bus Controller
13-83