MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1516

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
23.4.1.14 Power Management Power Down Counters Configuration
The power management power down counter configuration register (PMPDCCR) is shown in
Figure
23-24
Offset 0x088
Reset
Reset
19–23
24–31
Bits
W
W
R
R
23-14. The register contains bits that configure the power down counter used in deep sleep mode.
Figure 23-14. Power Management Power Down Counter Configuration Register (PMPDCCR)
16
0
0
RCNT_PRE
RCNT
Name
Register (PMPDCCR)
—
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
2
Reset count prescaler.
This field specifies the prescaler for the reset counter. Prescale value is 2
0x00 Reserved
0x01 1
0x02 2
0x03 4
0x04 8
...
0x09 256 (default)
...
0x1F 1,073,741,824
Reset count value.
When waking up from deep sleep power (VDD) is re-applied to a portion of the die. This value
determines the duration of the reset signal applied to this logic when power is re-applied. If
POWMGTCSR[DPSLP] = 0, this field has no effect. Reset is applied to the powered-off region
upon entering deep sleep. The RCNT value is copied into a decrementer that counts down at the
rate specified by the pre-scaler RCNT_FDR. When a wakeup event occurs, PMC will wait for the
POWER_OK signal to be asserted and the VRCNT counter to expire then begin decrementing
the reset counter. When the counter reaches 0 reset is removed. See also the description of
GCR[DEEPSLEEP_Z] in
WARNING: If the values placed in this register is too small, the reset may not assert long enough
to allow the chip to function properly. The default value is larger than the time it takes for the e500
PLLs to re-lock.
The default values for RCNT_PRE and RCNT are set to provide a minimum of 100 s reset time
(when used with platform clock up to 533 MHz).
Table 23-16. PMRCCR Field Descriptions (continued)
0
3
1
PDCNT_PRE
0
Section 23.4.1.27, “General Control Register
0
7
0
All zeros
—
Description
1
8
1
0
1
PDCNT
(GCR).”
0
Freescale Semiconductor
RCNT_PRE–1
Access: Read/Write
0
.
0
15
31
1