MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 646

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
13.1.3.1
The eLBC supports ratios of 4, 8, and 16 between the faster internal (system) clock and slower external
bus clock (LCLK[0:2]). This ratio is software programmable through the clock ratio register
(LCRR[CLKDIV]). This ratio affects the resolution of signal timing shifts in GPCM and FCM modes and
the interpretation of UPM array words in UPM mode. The bus clock is driven identically onto pins,
LCLK[0:2], to allow the clock load to be shared equally across a set of signal nets, thereby enhancing the
edge rates of the bus clock.
13.1.3.2
The eLBC provides the ID of a transaction source on external device pins. When those pins are selected,
the 5-bit internal ID of the current transaction source appears on MSRCID[0:4] whenever valid address or
data is available on the eLBC external pins. The reserved value of 0x1F, which indicates invalid address
or data, appears on the source ID pins at all other times. The combination of a valid source ID (any value
except 0x1F) and the value of external address latch enable (LALE) and data valid (MDVAL) facilitate
capturing useful debug data as follows:
The MSRCID[0:4] and MDVAL signals are multiplexed with other functions sharing the same external
pins. Refer to to learn how to enable the MSRCID/MDVAL pins.
13.2
Table 13-1
during assertion of HRESET, the PLL is initially unlocked, so the LCLK and LSYNC_OUT values are
likely to be unstable/jittery for several microseconds; after the PLL locks, stable clock signals are driven
on these signals.
13-4
•
•
If a valid source ID is detected on MSRCID[0:4] and LALE is asserted, a valid full 32-bit address
may be latched from LAD[0:26] and combined with LA[27:31].
If a valid source ID is detected on MSRCID[0:4] and MDVAL is asserted, valid data may be
latched from LAD.
LWE[1:3]/
LCS[1:7]
LBS[1:3]
External Signal Descriptions
LCS[0]
LFWE/
LWE0/
Name
LALE
LBS0
contains a list of external signals related to the eLBC and summarizes their function. Note that
eLBC Bus Clock and Clock Ratios
Source ID Debug Mode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Function(s)
Alternate
LFWE
LWE
LWE
LBS
LBS
—
—
—
Table 13-1. Signal Properties—Summary
GPCM
GPCM
Mode
UPM
UPM
FCM
—
—
—
External address latch enable
Chip select 0
Chip selects [1–7]
Write enable 0
Write enable
Byte (lane) select 0
Write enable 1–3
Byte (lane) select 1–3
Descriptions
Freescale Semiconductor
Signals
No. of
1
1
7
1
1
1
3
3
I/O
O
O
O
O
O