MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1236

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SATA Controller
Table 19-2
19.3.2.2
When a command is issued from the SATA controller to the device, the command is marked as active by
the hardware setting the appropriate command active bit of the CAR (shown in
command completes, the hardware clears the appropriate bit of the CAR.
For a device error, the CAR holds the command active bits at 1 for each command issued to the device in
error. When the host software clears the device error, the hardware in turn clears each of the commands
queued.
Table 19-3
19.3.2.3
When a command completes, the hardware sets the command completed bit for that command in the CCR
(shown in
bit for that command. When the software needs to acknowledge the reception of the command complete,
it can do so in two ways:
19-6
Offset 0x1_8000
Offset 0x1_8008
Reset
Reset
•
W
W
R
R
Writing a 1 to the command complete bit
31
31
Figure
describes the CQR fields.
describes the CAR fields.
Command Active Register (CAR)
Command Completed Register (CCR)
19-4) to a 1. The hardware also clears both the command queue and the command active
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
31–16
31–16
15–0
15–0
Bit
Bit
Figure 19-2. Command Queue Register (CQR)
Figure 19-3. Command Active Register (CAR)
—
—
Table 19-2. CQR Field Descriptions
Table 19-3. CAR Field Descriptions
Name
Name
CA n
CQ n
—
—
Reserved
Command n active bit
Reserved
Command n queue bit
All zeros
All zeros
16 15
16 15
Description
Description
CQ n
CA n
Figure
Freescale Semiconductor
19-3). Once a
Access: Read/Write
Access: Read only
0
0