MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1450

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
21.6.14.2.4 Host System Error
The host controller is a bus master and any interaction between the host controller and the system may
experience errors. The type of host error may be catastrophic to the host controller making it impossible
for the host controller to continue in a coherent fashion. Behavior for these types of errors is to halt the
host controller. Host-based error must result in the following actions:
Table 21-73
21.7
This section defines the interface data structures used to communicate control, status, and data between
device controller driver (DCD) software and the device controller. The data structure definitions in this
chapter support a 32-bit memory buffer address space. The interface consists of device queue heads and
transfer descriptors.
The data structures defined in the section are (from the device controller's perspective) a mix of read-only
and read/ writable fields. The device controller must preserve the read-only fields on all data structure
writes.
21-116
•
•
•
USBCMD[RS] is cleared.
USBSTS[SEI] and USBSTS[HCH] register are set
If the host system error enable bit, USBINTR[SEE] is set, the host controller issues a hardware
interrupt. This interrupt is not delayed to the next interrupt threshold.
Device Data Structures
summarizes the required actions taken on the various host errors.
After a host system error, software must reset the host controller using
USBCMD[RST] before re-initializing and restarting the host controller.
Software must ensure that no interface data structure reachable by the
device controller spans a 4K-page boundary.
Frame list pointer fetch (read)
siTD fetch (read)
siTD status write-back (write)
iTD fetch (read)
iTD status write-back (write)
qTD fetch (read)
qHD status write-back (write)
Data write
Data read
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Cycle Type
Table 21-73. Summary Behavior on Host System Errors
Master Abort
NOTE
NOTE
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Target Abort
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Data Phase
Parity
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
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