MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 350

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8.5.4.1
8.5.5
The DDR memory controller transfers the mode register set commands to the SDRAM array, and it uses
the setting of TIMING_CFG_0[MRS_CYC] for the Mode Register Set cycle time.
8-76
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•
•
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MCK[0], MCK[0]
MCK[1], MCK[1]
MCK[2], MCK[2]
If running with many devices, zero-delay PLL clock buffers, JEDEC-JESD82 standard, should be
used. These buffers were designed for DDR applications.
A 72 bit x 64 Mbytes DDR bank has 9-byte-wide DDR chips, resulting in 18 DDR chips in a
two-bank system. In this case, each MCK/MCK signal pair should drive exactly three devices.
PCB traces for DDR clock signals should be short, all on the same layer, and of equal length and
loading.
DDR SDRAM manufacturers provide detailed information on PCB layout and termination issues.
DDR SDRAM Mode-Set Command Timing
Clock Distribution
CS[0]
Figure 8-52. DDR SDRAM Clock Distribution Example for x8 DDR SDRAMs
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
DDR
A[15:0], BA[2:0], MRAS, MCAS, MWE, CKE
DQ[0:7], DQS[0], DM[0]
DQ[8:15], DQS[1], DM[1]
DQ[16:23], DQS[2], DM[2]
DQ[24:31], DQS[3], DM[3]
DQ[32:39], DQS[4], DM[4]
DQ[40:47], DQS[5], DM[5]
DQ[48:55], DQS[6], DM[6]
DQ[56:63], DQS[7], DM[7]
ECC[0:7], DQS[8], DM[8]
Freescale Semiconductor
CS[1]
MCK[3], MCK[3]
MCK[4], MCK[4]
MCK[5], MCK[5]