MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1396

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
between system software and host controller hardware. Information concerning the initialization of the
USB module is included in the following section; however, the full details of the EHCI specification are
beyond the scope of this document.
21.6.1
After initial power-on or host controller reset (hardware or through USBCMD[RST]), all of the operational
registers will be at their default values, as illustrated in Table 25. After a hardware reset, only the
operational registers not contained in the auxiliary power well will be at their default values.
In order to initialize the USB DR module, software should perform the following steps
At this point, the USB module is up and running and the port registers begin reporting device connects.
System software can enumerate a port through the reset process (where the port is in the enabled state). At
this point, the port is active with SOFs occurring down the enabled port enabled high-speed ports, but the
21-62
1. Set the controller mode to host mode. Optionally set USBMODE[SDIS] (streaming disable)
2. Optionally modify the BURSTSIZE register.
3. Program the PTS field of the PORTSC register if using a non-ULPI PHY.
4. Set CONTROL[USB_EN].
5. Write the appropriate value to the USBINTR register to enable the appropriate interrupts.
6. Write the base address of the periodic frame list to the PERIODICLIST BASE register. If there are
7. Write the USBCMD register to set the desired interrupt threshold, frame list size (if applicable) and
no work items in the periodic schedule, all elements of the periodic frame list should have their
T-Bits set.
turn the controller by setting the RS bit.
Operational Register
PERIODICLISTBASE
CTRLDSSEGMENT
ASYNCLISTADDR
CONFIGFLAG
Host Controller Initialization
USBINTR
FRINDEX
USBCMD
PORTSC
USBSTS
Transitioning from device mode to host mode requires a host controller reset
before modifying USBMODE.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-62. Default Values of Operational Register Space
0x0000_3000 (w/PPC cleared)
0x0008_0000 (0x0008_0B00 if asynchronous schedule park capability is set)
0x0000_1000
0x0000_0000
0x0000_0000
0x0000_0000
Undefined
Undefined
0x0000_0000
0x0000_2000 (w/PPC set);
NOTE
Default Value (After Reset)
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