MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1303

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MPC8536E-ANDROID

Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr

Specifications of MPC8536E-ANDROID

Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
20.4.12 Interrupt Signal Enable Register (IRQSIGEN)
IRQSIGEN selects which interrupt status is indicated to the host system as the interrupt. These status bits
all share the same interrupt line. Setting any of these bits enables an interrupt generation. The
corresponding status register bit generates an interrupt when the corresponding interrupt signal enable bit
is set.
Freescale Semiconductor
AC12EIEN
Offset: 0x038 (IRQSIGEN)
DMAEIEN
DEBEIEN
DTOEIEN
Reset
Reset
DCEIEN
CIEIEN
Field
0–2
4–6
10
11
12
W
W
3
7
8
9
R
R
16
0
Reserved
DMA error interrupt enable
0 Masked
1 Enabled
Reserved
Auto CMD12 error interrupt enable
0 Masked
1 Enabled
Reserved
Data end bit error interrupt enable
0 Masked
1 Enabled
Data CRC error interrupt enable
0 Masked
1 Enabled
Data timeout error interrupt enable
0 Masked
1 Enabled
Command index error interrupt enable
0 Masked
1 Enabled
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
Figure 20-14. Interrupt Signal Enable Register (IRQSIGEN)
DMAE
IEN
3
Table 20-19. IRQSIGEN Field Descriptions
4
22
6
AC12E
CINT
IEN
IEN
23
7
All zeros
All zeros
CRM
Description
IEN
24
8
DEBE
CINS
IEN
IEN
25
9
DCE
BRR
IEN
IEN
10
26
DTOE
BWR
Enhanced Secure Digital Host Controller
IEN
IEN
11
27
DINT
CIE
IEN
IEN
12
28
CEBE
BGE
IEN
IEN
13
29
Access: Read/Write
CCE
IEN
IEN
TC
14
30
CTOE
IEN
IEN
20-29
CC
15
31

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