MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1105

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
0xDD4–
0xDF4–
0xE14–
0xE38–
0x000–
0x000–
0xDCC
0xDDC
0xDEC
0xDD0
0xDE0
0xDE4
0xDE8
0xDFC
0xE0C
0xE1C
0xE2C
0xFFC
0xFFC
0xFFC
Offset
0xDF0
0xE00
0xE04
0xE08
0xE10
0xE20
0xE24
0xE28
0xE30
0xE34
PEXIWBEAR2—PCI Express inbound window base extended address
register 2
PEXIWAR2—PCI Express inbound window attributes register 2
Reserved
PEXITAR1—PCI Express inbound translation address register 1
Reserved
PEXIWBAR1—PCI Express inbound window base address register 1
Reserved
PEXIWAR1—PCI Express inbound window attributes register 1
Reserved
PEX_ERR_DR—PCI Express error detect register
Reserved
PEX_ERR_EN—PCI Express error interrupt enable register
Reserved
PEX_ERR_DISR—PCI Express error disable register
Reserved
PEX_ERR_CAP_STAT—PCI Express error capture status register
Reserved
PEX_ERR_CAP_R0—PCI Express error capture register 0
PEX_ERR_CAP_R1—PCI Express error capture register 1
PEX_ERR_CAP_R2—PCI Express error capture register 2
PEX_ERR_CAP_R3—PCI Express error capture register 3
Reserved
PCI Express Controller 2 registers
Note: All registers defined for PCI Express Controller 1 are also defined for PCI Express Controller 2; the offsets
PCI Express Controller 3 registers
Note: All registers defined for PCI Express Controller 1 are also defined for PCI Express Controller 3; the offsets
of PCI Express Controller 2 registers are the same except they have a different block base address.
of PCI Express Controller 3 registers are the same except they have a different block base address.
Table 17-3. PCI Express Memory-Mapped Register Map (continued)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PCI Express Controller 1 —Block Base Address 0x0_A000
PCI Express Controller 3—Block Base Address 0x0_B000
PCI Express Controller 2—Block Base Address 0x0_9000
PCI Express Controller 2 Memory-Mapped Registers
PCI Express Controller 3 Memory-Mapped Registers
PCI Express Error Management Registers
Register
Inbound Window 1
Access
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
—
—
—
—
—
—
—
0x0000_0000
0x20F4_4023
0x0000_0000
0x0000_0000
0x20F4_4023
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
PCI Express Interface Controller
Reset
—
—
—
—
—
—
—
—
—
17.3.5.2.5/17-27
17.3.5.2.6/17-28
17.3.5.2.3/17-26
17.3.5.2.4/17-27
17.3.5.2.6/17-28
17.3.6.1/17-30
17.3.6.2/17-32
17.3.6.3/17-34
17.3.6.4/17-36
17.3.6.5/17-36
17.3.6.6/17-38
17.3.6.7/17-40
17.3.6.8/17-42
Section/Page
—
—
—
—
17-9