MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1342

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
Table 21-5
21.3.1.4
HCCPARAMS identifies multiple mode control (time-base bit functionality) addressing capability.
Figure 21-5
21-8
Offset 0x108
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31–28
27–24
23–20
19–17
15–12
11–8
Bits
7–5
3–0
16
4
W
R
Offset 0x102
Reset 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0
31
W
N_PORTS
R
N_PCC
N_PTT
Name
N_CC
N_TT
31
provides bit descriptions for the HCSPARAMS register.
PPC
shows the HCCPARAMS register.
—
—
—
PI
Host Controller Capability Parameters (HCCPARAMS)
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
28 27
Figure 21-4. Host Controller Structural Parameters (HCSPARAMS)
Reserved, should be cleared.
Number of transaction translators. This is a non-EHCI field. This field indicates the number of embedded
transaction translators associated the module. This field is always 1. See
Transaction Translator Function.”
Ports per transaction translator. This is a non-EHCI field. The number of ports assigned to each
transaction translator. This is equal to N_PORTS.
Reserved, should be cleared.
Port indicators. Indicates whether the ports support port indicator control. Always 1.
1 The port status and control registers include a R/W field for controlling the state of the port indicator.
Number of companion controllers associated with the USB controller. Always 0.
controller. This field is always 0.
Reserved, should be cleared.
Power port control. Indicates whether the host controller supports port power control. It is always 1.
1 Ports have power port switches.
Number of ports. Number of physical downstream ports implemented for host applications. The value
of this field determines how many port registers are addressable in the operational register. Always 0x1.
Number ports per CC. This field indicates the number of ports supported per internal companion
Figure 21-5. Host Control Capability Parameters (HCCPARAMS)
N_TT
Table 21-5. HCSPARAMS Register Field Descriptions
—
24 23
N_PTT
20 19
—
16 15
17 16 15
PI
1 0 0 0 0 0 0 0 0 0 0 0
Description
N_CC
EECP
12 11
N_PCC
8
7
8
IST
7
Section 21.9.1, “Embedded
—
Freescale Semiconductor
0
4
5
PPC
—
Access: Read-only
3
0
Access: Read-only
4
1
ASP PFL ADC
1
2
0
3
N_PORTS
0
1
1
0
0
0
1
0