MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 711

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The timing parameters are summarized in
An example of minimum delay command timing appears in
and hold timing of command, address, and write data cycles with respect to LFWE assertion are all
identical, and that the minimum cycle extends for two LCLK clock cycles.
An example of relaxed command timing is shown in
Freescale Semiconductor
Figure 13-55. Example of FCM Command and Address Timing with Minimum Delay Parameters
1
Option Register Attributes
TRLX
In the parameters, SCY refers to a delay of OR n [SCY] clock cycles.
0
0
0
0
1
1
1
1
LCLK
(unused)
LFCLE
LFALE
LFWE
LAD[0:7]
TA
Table 13-36. FCM Command, Address, and Write Data Timing Parameters
CHT
0
0
1
1
0
0
1
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
CST
0
1
0
1
0
1
0
1
(for TRLX = 0, CHT = 0, CST = 0, SCY = 0)
command
t
CST
¼
¼
½
½
0
0
1
1
Table
t
Timing Parameter (LCLK Clock Cycles)
CHT
1½
1½
½
½
1
1
2
2
13-36.
address 0
Figure
2×SCY
2×SCY
2×SCY
2×SCY
SCY
SCY
SCY
SCY
t
WS
Figure
13-56.
address 1
½+2×SCY
½+2×SCY
1+2×SCY
1½+SCY
1¼+SCY
13-55. Note that the set-up, wait-state,
¾+SCY
1+SCY
2×SCY
t
WP
3+2×SCY
3+2×SCY
3+2×SCY
3+2×SCY
2+SCY
2+SCY
2+SCY
2+SCY
t
address 2
WC
Enhanced Local Bus Controller
1
4×(2+SCY)
4×(2+SCY)
4×(2+SCY)
4×(2+SCY)
8×(2+SCY)
8×(2+SCY)
8×(2+SCY)
8×(2+SCY)
t
ADL
13-69