MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 409

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9-36
9.3.6.5
The MSIDRs, shown in
Only one destination bit may be set; otherwise, behavior is undefined.
Table 9-37
Freescale Semiconductor
Offset MSIDR0: 0x1C10; MSIDR1: 0x1C30; MSIDR2: 0x1C50; MSIDR3: 0x1C70; MSIDR4:
Reset 0
12–15 PRIORITY Priority. Specifies the interrupt priority. The lowest priority is 0 and the highest priority is 15. A priority level
16–31
2–11
Bits Name
Bits
0
1
2
0
1
W
R
0x1C90; MSIDR5: 0x1CB0; MSIDR6: 0x1CD0; MSIDR7: 0x1CF0
EP CI0 CI1
1
0
CI0
CI1
VECTOR Vector (Affects only interrupts routed to int ). Contains the value returned when IACK is read and this
EP
Reserved in single-processor implementations.
Name
MSK
0
1
—
A
describes the bits of the MSIVPRs.
describes MSIDRn fields.
External signal. Allows interrupt to be serviced externally.
0 Interrupt is not routed to IRQ_OUT.
1 Interrupt is routed to IRQ_OUT for external servicing.
Critical interrupt 0.
0 Processor core 0 does not receive this interrupt.
1 Directs the shared message signaled interrupt to processor core 0 by causing the cint0 output signal from the
Critical interrupt 1. Reserved in single-processor implementations.
0 Processor core 1 does not receive this interrupt.
1 Directs the shared message signaled interrupt to processor core 1 by causing the cint1 output signal from the
Figure 9-35. Shared Message Signaled Interrupt Destination Registers (MSIDR n )
Shared Message Signaled Interrupt Destination Registers 0–7 (MSIDR n )
0
2
PIC to assert. See
PIC to assert. See
1
Mask. Mask interrupts from this source. MSK affects only interrupts routed to int .
0 An interrupt request is generated if the corresponding IPR bit is set.
1 Further interrupts from this source are disabled.
Activity. Indicates an interrupt has been requested or is in service. The VECTOR and PRIORITY values
should not be changed while this bit is set. Affects only interrupts routed to int .
0 No current interrupt activity associated with this source.
1 The interrupt field for this source is set in the IPR or ISR.
Reserved, should be cleared.
of 0 inhibits signalling of this interrupt to the core. Affects only interrupts routed to int .
interrupt resides in the corresponding interrupt request register (IRR) for that core, as shown in
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0 0
Figure
0
0 0
Section 9.1.2, “Interrupts to the Processor Core.”
Section 9.1.2, “Interrupts to the Processor Core.”
9-35, contain the destination fields for shared message signaled interrupts.
Table 9-36. MSIVPRn Field Descriptions
Table 9-37. MSIDR n Field Descriptions
0 0
0 0
0 0
Description
0 0
Description
—
0 0
0
0 0
Programmable Interrupt Controller (PIC)
0 0
0 0
0 0
Access: Read/Write
0 0
Figure
29
P1
30
0
9-49.
1
9-39
P0
31
1