MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 51

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
25.1.3.3
25.1.3.4
25.2
25.2.1
25.2.2
25.2.2.1
25.2.2.2
25.2.2.3
25.3
25.3.1
25.3.1.1
25.3.1.2
25.3.1.3
25.3.1.4
25.3.1.5
25.3.2
25.3.2.1
25.3.2.2
25.3.2.3
25.3.2.4
25.3.2.5
25.3.2.6
25.3.2.7
25.3.2.8
25.3.3
25.3.3.1
25.3.3.2
25.3.4
25.3.4.1
25.4
25.4.1
25.4.2
25.4.2.1
25.4.2.2
25.4.3
25.4.4
25.4.4.1
25.4.5
25.4.5.1
25.5
Freescale Semiconductor
External Signal Description ........................................................................................... 25-5
Memory Map/Register Definition ................................................................................. 25-9
Functional Description................................................................................................. 25-24
Initialization ................................................................................................................. 25-30
Overview.................................................................................................................... 25-5
Detailed Signal Descriptions ..................................................................................... 25-6
Watchpoint Monitor Register Descriptions ............................................................. 25-10
Trace Buffer Register Descriptions.......................................................................... 25-15
Context ID Registers................................................................................................ 25-22
Trigger Out Function ............................................................................................... 25-23
Source and Target ID ............................................................................................... 25-24
DDR SDRAM Interface Debug............................................................................... 25-25
Local Bus Interface Debug ...................................................................................... 25-26
Watchpoint Monitor ................................................................................................. 25-26
Trace Buffer ............................................................................................................. 25-27
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Watchpoint Monitor Modes ................................................................................... 25-4
Trace Buffer Modes ............................................................................................... 25-4
Debug Signals—Details......................................................................................... 25-6
Watchpoint Monitor Trigger Signals—Details...................................................... 25-7
Test Signals—Details............................................................................................. 25-8
Watchpoint Monitor Control Registers 0–1 (WMCR0, WMCR1)...................... 25-10
Watchpoint Monitor Address Register (WMAR)................................................ 25-12
Watchpoint Monitor Transaction Mask Register (WMTMR) ............................. 25-13
Watchpoint Monitor Status Register (WMSR) .................................................... 25-15
Trace Buffer Control Registers (TBCR0, TBCR1) ............................................. 25-15
Trace Buffer Address Register (TBAR) .............................................................. 25-18
Trace Buffer Address Mask Register (TBAMR)................................................. 25-18
Trace Buffer Transaction Mask Register (TBTMR)............................................ 25-19
Trace Buffer Status Register (TBSR) .................................................................. 25-19
Trace Buffer Access Control Register (TBACR) ................................................ 25-20
Trace Buffer Access Data High Register (TBADHR)......................................... 25-21
Trace Buffer Access Data Register (TBADR)..................................................... 25-21
Programmed Context ID Register (PCIDR) ........................................................ 25-22
Current Context ID Register (CCIDR) ................................................................ 25-23
Trigger Out Source Register (TOSR) .................................................................. 25-23
Debug Information on Debug Pins ...................................................................... 25-25
Debug Information on ECC Pins......................................................................... 25-25
Watchpoint Monitor Performance Monitor Events ............................................. 25-26
Traced Data Formats (as a Function of TBCR1[IFSEL]).................................... 25-27
Watchpoint Monitor Address Mask Register (WMAMR) ................................. 25-13
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