MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 219

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Multiprocessor
functionality
R1 and R2 data
bus parity
Dynamic bus
snooping
Device specific
definition for
TCR[WRC]
SPE and
floating-point
categories
PIR value
PVR value
SVR value
TCR (timer
control register ()
HID0
implementation
Table 5-1. Differences Between the e500 Core and the PowerQUICC III Core Implementation (continued)
Feature
Because PowerQUICC III is designed for a uniprocessor environment, the following e500 functionality is not
implemented:
R1 and R2 data bus parity are disabled on PowerQUICC III devices. HID1[R1DPE,R2DPE] are reserved.
The PowerQUICC III devices do not perform dynamic bus snooping as described here. That is, when the e500
core is in core-stopped state (which is the state of the core when the PowerQUICC III device is in either the
nap or sleep state), the core is not awakened to perform snoops on global transactions.
PowerQUICC III devices define values for 00, 01, 10, and 11, as described in
Details
The SPE (which includes the embedded vector and scalar floating-point instructions) will not be implemented
in the next generation of PowerQUICC devices. Freescale Semiconductor strongly recommends that use of
these instructions be confined to libraries and device drivers. Customer software that uses these instructions
at the assembly level or that uses SPE or floating-point intrinsics will require rewriting for upward compatibility
with next generation PowerQUICC devices.
The e500v2 core implements SPE double-precision floating-point instructions.
Freescale Semiconductor offers a libcfsl_e500 library that uses SPE instructions. Freescale Semiconductor
will also provide future libraries to support next generation PowerQUICC devices.
Note that in the Power ISA, MSR[SPE] and ESR[SPE] are renamed to MSR[SPV] and ESR[SPV].
The PIR value is all zeros on PowerQUICC III devices.
The PVR reset value is 0x80 nn _ nnnn. See
PVR[VERSION] = 0x80 nn
PVR[REVISION] = 0x nnnn
The SVR reset value is 0x80 nn _ nnnn. See
TCR[WRC] is defined more specifically for the implementation of the core in the integrated device.
Watchdog timer reset control. This value is written into TSR[WRS] when a watchdog event occurs. WRC may
be set by software but cannot be cleared by software, except by a software-induced reset. Once written to a
non-zero value, WRC may no longer be altered by software.
00 No watchdog timer reset can occur.
01 Force processor checkstop on second timeout of watchdog timer
10 Assert processor reset output ( core_hreset_req ) on second timeout of watchdog timer
11 Reserved
SEL_TBCLK. Selects time base clock. If this bit is set and the time base is enabled, the time base is based
on the TBCLK input, which on the PowerQUICC III devices is RTC.
• The memory coherence bit, M, which is controlled through MAS2[M] and MAS4[MD] has no effect.
• HID1[ABE] has meaning only in that it must be set to ensure that cache and TLB management instructions
• Dynamic snooping does not occur in power-stopped state (see the note below in the entry for dynamic bus
operate properly with respect to the L2 cache.
snooping).
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
in this table.
Register Model Integration Details
PowerQUICC III Implementation
Table 5-2
Table 5-2
for specific values.
for specific values.
Register Model Integration
e500 Core Integration Details
5-5