MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1546

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
blocks that respond to power-down requests. The mode-transition protocol is executes automatically under
these conditions and is shown in
The column in
to the external masters that can write to the POWMGTCSR that resides in the global utilities block. For
the MPC8536E, these are the PCI interfaces. However, note that the core can also write to POWMGTCSR
and, in this case, can initiate power management through the global utilities block.
As shown in
core_stop, or core_tben inputs from the MPC8536Es power management logic. These inputs may be
prompted by the core (by setting the NAP, DOZE, or SLEEP bits in the HID0 when enabled by setting
MSR[WE]) or by an external master (by setting POWMGTCSR[DOZ,SLP,DPSLP].
Figure 23-35
When enabled, (HID0[TBEN] = 1), the clock source is either the CCB clock divided by eight (the default)
or a synchronized version of the RTC input.
23.5.1.9
Whether low-power modes are automatically re-enabled after an interrupt is processed differs depending
on whether the low power mode was entered due to a write to the core MSR[WE] bit or the low power
mode was entered due to a write to POWMGTCSR.
23.5.1.9.1
When an interrupt is asserted to the CPU, the core complex saves portions of the MSR to MCSRR1,
CSRR1, or SRR1 (depending on the type of interrupt), and restores those values on return from the routine.
MSR[WE], which gates the doze, nap, and sleep power management outputs (internal device signals) from
23-54
Low-Power Mode
Deep Sleep
Sleep
Doze
Nap
Figure
Interrupts and Power Management (e500)
shows how all the clocking to the core timer facilities is disabled by clearing HID0[TBEN].
Table 23-37. Power Management Entry Protocol and Initiating Functional Units
Table 23-37
Interrupts and Power Management Controlled by MSR[WE] (e500)
1. Assert core_halt input to core.
2. Wait for core_halted handshake from core.
3. Negate ASLEEP and READY
1. Follow doze protocol
2. Assert core_stop input to core.
3. Wait for core_stopped handshake from core.
4. Negate ASLEEP and READY
1. Follow doze protocol; send stop requests to rest of device.
2. Follow nap protocol.
3. Wait for all interfaces to acknowledge stop requests.
4. Assert ASLEEP, negate READY, power down all clocks except to PIC unit
1. Follow doze protocol; send stop requests to rest of device.
2. Follow nap protocol.
3. Follow sleep protocol steps 1-3
4. Isolate inputs and outputs of core complex (e500 and L2)
5. Remove power to the core complex
6. Assert ASLEEP, negate READY, power down all clocks except to PIC unit
and units generating wakeup events.
and units generating wakeup events.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
23-35, the e500 core enters low-power modes only in response to the core_halt,
showing the global utilities block as initiating a low-power mode corresponds
Figure 23-35
Entry Protocol
and described in
Table
23-37.
Initiating Functional Unit
Global Utilities
Freescale Semiconductor
—
Core