MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1037

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.3
The PCI controller supports the following two types of registers:
16.3.1
The PCI memory mapped registers are accessed by reading and writing to an address comprised of the base
address (specified in the CCSRBAR on the local side or the PCSRBAR on the PCI side) plus the block
base address, plus the offset of the specific register to be accessed. Note that all memory-mapped registers
(except the PCI configuration data register, PCI CFG_DATA) must only be accessed as 32-bit quantities.
Table 16-3
Freescale Semiconductor
0x00C–
0xBFC
Offset
0xC00
0xC04
0x000
0x004
0x008
•
•
PCI_CLK
Signal
Memory-mapped registers—these registers control PCI address translation, PCI error
management, and PCI configuration register access. These registers are described in
Section 16.3.1, “PCI Memory-Mapped Registers,”
PCI configuration registers contained within the PCI configuration header—these registers are
specified by the PCI bus specification for every PCI device. These registers are described in
Section 16.3.2, “PCI Configuration Header,”
Memory Map/Register Definitions
CFG_ADDR—PCI configuration address
CFG_DATA—PCI configuration data
INT_ACK—PCI interrupt acknowledge
Reserved
POTAR0—PCI outbound window 0 (default) translation address
register
POTEAR0—PCI outbound window 0 (default) translation extended
address register
lists the memory-mapped registers.
PCI Memory-Mapped Registers
Table 16-2. PCI Interface Signals—Detailed Signal Descriptions (continued)
I/O
I PCI clock is an independent clock that may be used for the PCI interface. If used the PCI operation is
PCI Controller Memory-Mapped Registers—Block Base Address 0x0_8000
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
asynchronous with respect to SYSCLK and the platform clock. In order to used this signal as the PCI
clock source, it must be designated during POR configuration. See the reset chapter for POR details
regarding clock selection as well as proper PCI frequency selection.
Timing Assertion/Negation—See the device Hardware Specification for specific timing information.
Table 16-3. PCI Memory-Mapped Register Map
PCI ATMU Registers—Outbound and Inbound
0xC00–0xC3C–Outbound Window 0 (default)
Register
PCI Configuration Access Registers
and its subsections.
Description
and its subsections.
Access
R/W
R/W
R/W
R/W
—
R
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
16.3.1.1.1/16-14
16.3.1.1.2/16-15
16.3.1.1.3/16-15
16.3.1.2.1/16-16
16.3.1.2.2/16-16
PCI Bus Interface
Section/page
—
16-11