MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1018

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DMA Controller
15.4.1.8
If operating in stride mode, the stride size defines the amount of data to transfer before jumping to the next
quantity of data as specified by the stride distance. The stride distance is added to the current base address
to point to the next quantity of data to be transferred.
parameters. As shown, each time the stride distance is added to the base address, the resulting address
becomes the new base address. This sequence repeats until the amount of data transferred equals the
transfer size.
15.4.2
The DMA can be used to achieve data transfers across the entire memory map. Note that a single DMA
transfer in any of the direct or chaining modes must not cross a 16GB (34-bit) address boundary.
15.4.3
On a transfer error (uncorrectable ECC errors on memory accesses, parity errors on local bus or PCI,
address mapping errors, for example), the DMA halts by setting SRn[TE] and generates an interrupt if
MRn[EIE] is set. On a programming error, the DMA sets SRn[PE] and generates an interrupt if MRn[EIE]
is set. The DMA controller detects the following programming errors:
15-32
MR n [CS] SR n [CB] SR n [TE] MR n [CC]
•
•
•
•
1
1
1
1
Base Address
Transfer started with a byte count of zero
Stride transfer started with a stride size of zero
Transfer started with a priority of three
Illegal type, defined by SATRn[SREADTTYPE] and DATRn[DWRITETTYPE], used for the
transfer.
DMA Transfer Interfaces
DMA Errors
0
0
1
1
Illustration of Stride Size and Stride Distance
Stride Distance
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Stride Size
1
1
0
0
Figure 15-24. Stride Size and Stride Distance
Table 15-23. Channel State Table (continued)
0
1
0
1
Error occurred during transfer
Channel remains in error halt state
Transfer in progress
Continue after reaching the end of list/link, or the first descriptor fetch after channel
continue
New Base Address
Figure 15-24
Channel State
illustrates the stride size and distance
New Base Address
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