MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1555

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 24
Device Performance Monitor
This chapter describes the device performance monitor facility, which can be used to monitor and optimize
performance. The e500 core implements a separate performance monitor for strictly core-related behavior,
such as instruction timing and L1 cache operations. This is described in the PowerPC e500 Core Reference
Manual (Freescale Document Order No. E500CORERM).
Section 24.4.7, “Performance Monitor Events,”
to the individual chapters for a better understanding of these events.
24.1
The device-level performance monitor facility that can be used to monitor and record selected behaviors
of the integrated device. Although the performance monitor described here is similar in many respects to
the performance monitor facility implemented on the e500 core, it differs in that it is implemented using
memory-mapped registers and it counts events outside the e500 core, for example, PCI, DDR, and L2
cache events.
Performance monitor counters (PMC0–PMC9) are used to count events selected by the performance
monitor local control registers. PMC0 is a 64-bit counter specifically designated to count cycles.
PMC1–PMC9 are 32-bit counters that can monitor 64 counter-specific events in addition to counting 64
reference events.
The benefits of the on-chip performance monitor are numerous, and include the following:
Freescale Semiconductor
•
•
•
Because some systems or software environments are not easily characterized by signal traces or
benchmarks, the performance monitor can be used to understand the device’s behavior in any
system or software environment.
The performance monitor facility can be used to aid system developers when bringing up and
debugging systems.
System performance can be increased by monitoring memory hierarchy behavior. This can help to
optimize algorithms used to schedule or partition tasks and to refine the data structures and
distribution used by each task.
Introduction
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
briefly describes the events that can be monitored. Refer
24-1